A realizable driving point model for on-chip interconnect with inductance. - Chandramouli V. Kashyap; Byron Krauter (DAC, 2000)

An "Effective" Capacitance Based Delay Metric for RC Interconnect. - Chandramouli V. Kashyap; Charles J. Alpert; Anirudh Devgan (ICCAD, 2000)

A two moment RC delay metric for performance optimization. - Charles J. Alpert; Anirudh Devgan; Chandramouli V. Kashyap (ISPD, 2000)

RC delay metrics for performance optimization. - Charles J. Alpert; Anirudh Devgan; Chandramouli V. Kashyap (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. - Masud H. Chowdhury; Yehea I. Ismail; Chandramouli V. Kashyap; Byron Krauter (ISCAS (4), 2002)

PERI: a technique for extending delay and slew metrics to ramp inputs. - Chandramouli V. Kashyap; Charles J. Alpert; Frank Liu 001; Anirudh Devgan (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

Delay and slew metrics using the lognormal distribution. - Charles J. Alpert; Frank Liu 001; Chandramouli V. Kashyap; Anirudh Devgan (DAC, 2003)

Block-based Static Timing Analysis with Uncertainty. - Anirudh Devgan; Chandramouli V. Kashyap (ICCAD, 2003)

Realizable reduction of RLC circuits using node elimination. - Masud H. Chowdhury; Chirayu S. Amin; Yehea I. Ismail; Chandramouli V. Kashyap; Byron Krauter (ISCAS (3), 2003)

Closed form expressions for extending step delay and slew metrics to ramp inputs. - Chandramouli V. Kashyap; Charles J. Alpert; Frank Liu 001; Anirudh Devgan (ISPD, 2003)

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. - Charles J. Alpert; Chris C. N. Chu; Gopal Gandham; Milos Hrkic; Jiang Hu; Chandramouli V. Kashyap; Stephen T. Quay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Closed-form delay and slew metrics made easy. - Charles J. Alpert; Frank Liu 001; Chandramouli V. Kashyap; Anirudh Devgan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. - Chandramouli V. Kashyap; Charles J. Alpert; Frank Liu 001; Anirudh Devgan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A delay metric for RC circuits based on the Weibull distribution. - Frank Liu 001; Chandramouli V. Kashyap; Charles J. Alpert (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis. - Haihua Su; David Widiger; Chandramouli V. Kashyap; Frank Liu 001; Byron Krauter (DAC, 2005)

A multi-port current source model for multiple-input switching effects in CMOS library cells. - Chirayu S. Amin; Chandramouli V. Kashyap; Noel Menezes; Kip Killpack; Eli Chiprout (DAC, 2006)

Fast Interconnect and Gate Timing Analysis for Performance Optimization. - Soroush Abbaspour; Massoud Pedram; Amir H. Ajami; Chandramouli V. Kashyap (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Silicon Speedpath Measurement and Feedback into EDA flows. - Kip Killpack; Chandramouli V. Kashyap; Eli Chiprout (DAC, 2007)

A nonlinear cell macromodel for digital applications. - Chandramouli V. Kashyap; Chirayu S. Amin; Noel Menezes; Eli Chiprout (ICCAD, 2007)

A framework for block-based timing sensitivity analysis. - Sanjay V. Kumar; Chandramouli V. Kashyap; Sachin S. Sapatnekar (DAC, 2008)

A "true" electrical cell model for timing, noise, and power grid verification. - Noel Menezes; Chandramouli V. Kashyap; Chirayu S. Amin (DAC, 2008)

Silicon feedback to improve frequency of high-performance microprocessors: an overview. - Chandramouli V. Kashyap; Pouria Bastani; Kip Killpack; Chirayu S. Amin (ICCAD, 2008)

Quantifying robustness metrics in parameterized static timing analysis. - Khaled R. Heloue; Chandramouli V. Kashyap; Farid N. Najm (ICCAD, 2009)

Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. - Debasish Das; Kip Killpack; Chandramouli V. Kashyap; Abhijit Jas; Hai Zhou 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Guest Editors' Introduction Challenges and Opportunities in Analog/Mixed-Signal CAD. - Xin Li 001; Chandramouli V. Kashyap; Chris J. Myers (IEEE Des. Test, 2016)

MLParest: Machine Learning based Parasitic Estimation for Custom Circuit Design. - Brett Shook; Prateek Bhansali; Chandramouli V. Kashyap; Chirayu Amin; Siddhartha Joshi (DAC, 2020)

DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. - Ahmet Faruk Budak; Prateek Bhansali; Bo Liu 003; Nan Sun 001; David Z. Pan; Chandramouli V. Kashyap (DAC, 2021)

Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables. - Subhadip Ghosh; Endalk Y. Gebru; Chandramouli V. Kashyap; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2025)