Model Development and Verification for High Level Analog Blocks. - Chandramouli Visweswariah; Rakesh Chadha; Chin-Fu Chen (DAC, 1988)

Incorporation of Inductors in Piecewise Approximate Circuit Simulation. - Chandramouli Visweswariah; Peter Feldmann; Ronald A. Rohrer (ICCAD, 1990)

Efficient Simulation of Bipolar Digital ICs. - Chandramouli Visweswariah; Ronald A. Rohrer (DAC, 1991)

Piecewise approximate circuit simulation. - Chandramouli Visweswariah; Ronald A. Rohrer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

M3-a multilevel mixed-mode mixed A/D simulator. - Rakesh Chadha; Chandramouli Visweswariah; Chin-Fu Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Incremental Event-Driven Simulation of Digital FET Circuits. - Chandramouli Visweswariah; Jalal A. Wehbeh (DAC, 1993)

Inaccuracies in power estimation during logic synthesis. - Daniel Brand; Chandramouli Visweswariah (ICCAD, 1996)

Optimization of custom MOS circuits by transistor sizing. - Andrew R. Conn; Paula K. Coulman; Ruud A. Haring; Gregory L. Morrill; Chandramouli Visweswariah (ICCAD, 1996)

Circuit optimization via adjoint Lagrangians. - Andrew R. Conn; Ruud A. Haring; Chandramouli Visweswariah; Chai Wah Wu (ICCAD, 1997)

Optimization techniques for high-performance digital circuits. - Chandramouli Visweswariah (ICCAD, 1997)

JiffyTune: circuit optimization using time-domain sensitivities. - Andrew R. Conn; Paula K. Coulman; Ruud A. Haring; Gregory L. Morrill; Chandramouli Visweswariah; Chai Wah Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation. - Andrew R. Conn; Ibrahim M. Elfadel; W. W. Molzen; P. R. O'Brien; Philip N. Strenski; Chandramouli Visweswariah; C. B. Whan (DAC, 1999)

Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation. - Chandramouli Visweswariah; Andrew R. Conn (ICCAD, 1999)

Noise considerations in circuit optimization. - Chandramouli Visweswariah; Ruud A. Haring; Andrew R. Conn (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Overview of continuous optimization advances and applications to circuit tuning. - Andrew R. Conn; Chandramouli Visweswariah (ISPD, 2001)

Uncertainty-aware circuit optimization. - Xiaoliang Bai; Chandramouli Visweswariah; Philip N. Strenski (DAC, 2002)

Is statistical timing statistically significant? - Richard Goldman; Kurt Keutzer; Clive Bittlestone; Ahsan Bootehsaz; Shekhar Y. Borkar; E. Chen; Louis Scheffer; Chandramouli Visweswariah (DAC, 2004)

First-order incremental block-based statistical timing analysis. - Chandramouli Visweswariah; K. Ravindran; Kerim Kalafala; Steven G. Walker; S. Narayan (DAC, 2004)

Large-scale nonlinear optimization in circuit tuning. - Andreas Wächter; Chandramouli Visweswariah; Andrew R. Conn (Future Gener. Comput. Syst., 2005)

Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. - Jochen A. G. Jess; Kerim Kalafala; Srinath R. Naidu; Ralph H. J. M. Otten; Chandramouli Visweswariah (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

First-Order Incremental Block-Based Statistical Timing Analysis. - Chandramouli Visweswariah; K. Ravindran; Kerim Kalafala; Steven G. Walker; S. Narayan; Daniel K. Beece; Jeff Piaget; Natesan Venkateswaran; Jeffrey G. Hemmett (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)