Design of a 1-Volt and µ-power SARADC for Sensor Network Application. - Sang-Hyun Cho; Chang-Kyo Lee; Jong-In Song (ISCAS, 2007)

A Time-interleaved Flash-SAR Architecture for High Speed A/D Conversion. - Ba Sung; Sang-Hyun Cho; Chang-Kyo Lee; Jong-In Kim; Seung-Tak Ryu (ISCAS, 2009)

A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction. - Sang-Hyun Cho; Chang-Kyo Lee; Jong-Kee Kwon; Seung-Tak Ryu (CICC, 2010)

A 550-μW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction. - Sang-Hyun Cho; Chang-Kyo Lee; Jong-Kee Kwon; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2011)

A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm. - Sang-Hyun Cho; Chang-Kyo Lee; Sang-Gug Lee 001; Seung-Tak Ryu (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design. - Chang-Kyo Lee; Wan Kim; Hyun-Wook Kang; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Real-time 3D human pose recognition from reconstructed volume via voxel classifiers. - ByungIn Yoo; Changkyu Choi; Jae-Joon Han; Chang-Kyo Lee; Wonjun Kim; Sungjoo Suh; Dusik Park; Junmo Kim 002 (Three-Dimensional Image Processing, Measurement (3DIPM), and Applications, 2014)

A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications. - Ghil-Geun Oh; Chang-Kyo Lee; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface. - Chang-Kyo Lee; Min-Su Ahn; Daesik Moon; Kiho Kim; Yoon-Joo Eom; Won-Young Lee; Jongmin Kim; Sanghyuk Yoon; Baekkyu Choi; Seokhong Kwon; Joon-Young Park; Seung-Jun Bae; et al. (VLSIC, 2015)

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Gil-Hoon Cha; Jin-Hyeok Baek; Daesik Moon; Yoon-Joo Eom; Tae-Sung Kim; Hyunyoon Cho; Young Hoon Son; Seonghwan Kim 002; et al. (A-SSCC, 2017)

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme. - Chang-Kyo Lee; Yoon-Joo Eom; Jin-Hee Park; Junha Lee; Hye-Ran Kim; Kihan Kim; Young Choi; Ho-Jun Chang; Jonghyuk Kim; Jong-Min Bang; Seungjun Shin; Hanna Park; et al. (ISSCC, 2017)

Performance Test of LTE-R Railway Wireless Communication at High-Speed (350 km/h) Environments. - Mahn-Suk Yoon; Sung-Hun Lee; Chang-Kyo Lee; Soo-Hyun Cho; Wan-Jin Ko (ICUFN, 2018)

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. - Ki Chul Chun; Yonggyu Chu; Jin-Seok Heo; Tae-Sung Kim; Soohwan Kim; Hui-Kap Yang; Mi-Jo Kim; Chang-Kyo Lee; Ju-Hwan Kim; Hyunchul Yoon; Chang-Ho Shin; Sang-uhn Cha; et al. (ISSCC, 2018)

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process. - Jin-Hyeok Baek; Chang-Kyo Lee; Kiho Kim; Daesik Moon; Gil-Hoon Cha; Jin-Seok Heo; Min-Su Ahn; Dong-Ju Kim; Jae-Joon Song; Seokhong Kwon; Jongmin Kim; Kyung-Soo Kim; et al. (VLSI Circuits, 2018)

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Jin-Hyeok Baek; Gil-Hoon Cha; Daesik Moon; Dong-Hun Lee; Jong-Wook Park; Seunseob Lee; Si-Hyeong Cho; Young-Ryeol Choi; et al. (IEEE J. Solid State Circuits, 2018)

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. - Kyung-Soo Ha; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; Jin-Hun Jang; Hyong-Ryol Hwang; Hyung-Joon Chi; Junghwan Park; Seungjun Shin; Dukha Park; Sang-Yun Kim 001; Sukhyun Lim; et al. (ISSCC, 2019)

A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration. - Jin-Seok Heo; Kihan Kim; Dong-Hoon Lee; Chang-Kyo Lee; Daesik Moon; Kiho Kim; Jin-Hyeok Baek; Sung-Woo Yoon; Hui-Kap Yang; Kyungryun Kim; Youngjae Kim; Bokgue Park; et al. (VLSI Circuits, 2019)

Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC. - Chang-Kyo Lee; Seung-Tak Ryu (IET Circuits Devices Syst., 2019)

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. - Hyung-Joon Chi; Chang-Kyo Lee; Junghwan Park; Jin-Seok Heo; Jaehoon Jung; Dongkeon Lee; Dae-Hyun Kim 003; Dukha Park; Kihan Kim; Sang-Yun Kim 001; Jinsol Park; Hyunyoon Cho; et al. (ISSCC, 2020)

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. - Kyung-Soo Ha; Seungseob Lee; Youn-Sik Park; Hyuck-Joon Kwon; Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Jung-Bae Lee; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; et al. (IEEE J. Solid State Circuits, 2020)

Interpretation of Impact-Echo Testing Data from a Fire-Damaged Reinforced Concrete Slab Using a Discrete Layered Concrete Damage Model. - Chang-Kyo Lee; Seong-Hoon Kee; Jun Won Kang; Byong-Jeong Choi; Jin Woo Lee (Sensors, 2020)

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. - Chang-Kyo Lee; Hyung-Joon Chi; Jin-Seok Heo; Junghwan Park; Jin-Hun Jang; Dongkeon Lee; Jaehoon Jung; Dong-Hun Lee; Dae-Hyun Kim 003; Kihan Kim; Sang-Yun Kim 001; Dukha Park; et al. (IEEE J. Solid State Circuits, 2021)

Q-Learning based Collision Avoidance for 802.11 Stations with Maximum Requirements. - Chang-Kyo Lee; Dong Hyun Lee; Junseok Kim; Xiaoying Lei; Seung Hyong Rhee (KSII Trans. Internet Inf. Syst., 2023)