A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution. - Chang-Kyung Seong; Seung-Woo Lee; Woo-Young Choi (IEICE Trans. Electron., 2007)

A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator. - Chang-Kyung Seong; Seung-Woo Lee; Woo-Young Choi (IEICE Trans. Commun., 2008)

A New Network Synchronizer Using Phase Adjustment and Feedforward Filtering Based on Low-Cost Crystal Oscillators. - Chang-Kyung Seong; Seung-Woo Lee; Woo-Young Choi (IEEE Trans. Instrum. Meas., 2010)

A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms. - Wang-Soo Kim; Chang-Kyung Seong; Woo-Young Choi (ISSCC, 2011)

A 5.4-Gbit/s Adaptive Continuous-Time Linear Equalizer Using Asynchronous Undersampling Histograms. - Wang-Soo Kim; Chang-Kyung Seong; Woo-Young Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A 10-Gb/s Adaptive Look-Ahead Decision Feedback Equalizer With an Eye-Opening Monitor. - Chang-Kyung Seong; Jinsoo Rhim; Woo-Young Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2012)