An effective analytical 3D placer in monolithic 3D IC designs. - Yande Jiang; Xu He; Chang Liu 019; Yang Guo 003 (ASICON, 2015)

Analysis of SET Reconvergence and Hardening in the Combinational Circuit Using a SAT-Based Method. - Chang Liu 019; Long Zhang 004; Xu He; Yang Guo 003 (IEEE Access, 2018)

Detailed placement for pulse quenching enhancement in anti-radiation combinational circuit design. - Chang Liu 019; Xu He; Bin Liang; Yang Guo 003 (Integr., 2018)

一种基于SAT求解器的组合电路重汇聚现象分析方法 (Reconvergence Phenomena Analysis Method in Combinational Circuits Based on SAT Solver). - Lujie Zhang; Chang Liu 019; Long Zhang 004; Yang Guo 003 (计算机科学, 2019)

Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions. - Yaohua Wang; Chen Li 015; Chang Liu 019; Sheng Liu 001; Yuanwu Lei; Jian Zhang 022; Yang Zhang; Yang Guo 003 (CCF Trans. High Perform. Comput., 2021)

Accurate timing prediction at placement stage with look-ahead RC network. - Xu He; Zhiyong Fu; Yao Wang 002; Chang Liu 019; Yang Guo 003 (DAC, 2022)

A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits. - Xu He; Yao Wang 002; Chang Liu 019; Qiang Wu 015; Juan Luo; Yang Guo 003 (ACM Trans. Design Autom. Electr. Syst., 2023)

SI-Aware Wire Timing Prediction at Pre-Routing Stage with Multi-Corner Consideration. - Yushan Wang; Xu He; Renjun Zhao; Yao Wang 002; Chang Liu 019; Yang Guo 003 (ASP-DAC, 2025)