GPE: A New Representation for VLSI Floorplan Problem. - Chang-Tzu Lin; De-Sheng Chen; Yiwen Wang 003 (ICCD, 2002)

Non-slicing floorplans with boundary constraints using generalized polish expression. - De-Sheng Chen; Chang-Tzu Lin; Yiwen Wang 003 (ASP-DAC, 2003)

Robust fixed-outline floorplanning through evolutionary search. - Chang-Tzu Lin; De-Sheng Chen; Yiwen Wang 003 (ASP-DAC, 2004)

Modem floorplanning with abutment and fixed-outline constraints. - Chang-Tzu Lin; De-Sheng Chen; Yiwen Wang 003; Hsin-Hsien Ho (ISCAS (6), 2005)

Modern Floorplanning with Boundary and Fixed-outline Constraints via Genetic Clustering Algorithm. - Chang-Tzu Lin; De-Sheng Chen; Yiwen Wang 003 (J. Circuits Syst. Comput., 2006)

Noise-Aware Floorplanning for Fast Power Supply Network Design. - Chang-Tzu Lin; Tai-Wei Kung; De-Sheng Chen; Yiwen Wang 003; Ching-Hwa Cheng (ISCAS, 2007)

Fixed-outline floorplanning using robust evolutionary search. - De-Sheng Chen; Chang-Tzu Lin; Yiwen Wang 003; Ching-Hwa Cheng (Eng. Appl. Artif. Intell., 2007)

CAD reference flow for 3D via-last integrated circuits. - Chang-Tzu Lin; Ding-Ming Kwai; Yung-Fa Chou; Ting-Sheng Chen; Wen Ching Wu (ASP-DAC, 2010)

3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvement. - Ding-Ming Kwai; Chang-Tzu Lin (ISQED, 2011)

Hierarchical power network synthesis for multiple power domain designs. - Chieh-Jui Lee; Shih-Ying Liu; Chuan-Chia Huang; Hung-Ming Chen; Chang-Tzu Lin; Chia-Hsin Lee (ISQED, 2012)

3-D centric technology and realization with TSV. - Chang-Tzu Lin; Chia-Hsin Lee; Tsu-Wei Tseng; Ding-Ming Kwai; Yung-Fa Chou (VLSI-DAT, 2012)

I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs. - Chi-Wen Pan; Yu-Min Lee; Pei-Yu Huang; Chi-Ping Yang; Chang-Tzu Lin; Chia-Hsin Lee; Yung-Fa Chou; Ding-Ming Kwai (ASP-DAC, 2013)

Effective power network prototyping via statistical-based clustering and sequential linear programming. - Shih-Ying Sean Liu; Chieh-Jui Lee; Chuan-Chia Huang; Hung-Ming Chen; Chang-Tzu Lin; Chia-Hsin Lee (DATE, 2013)

Enabling inter-die co-optimization in 3-D IC with TSVs. - Chang-Tzu Lin; Tsu-Wei Tseng; Yung-Fa Chou; Chia-Hsin Lee; Ding-Ming Kwai (VLSI-DAT, 2013)

Improving power delivery network design by practical methodologies. - Chia-Chi Huang; Chang-Tzu Lin; Wei-Syun Liao; Chieh-Jui Lee; Hung-Ming Chen; Chia-Hsin Lee; Ding-Ming Kwai (ICCD, 2014)

A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage. - Tsu-Wei Tseng; Chang-Tzu Lin; Chia-Hsin Lee; Yung-Fa Chou; Ding-Ming Kwai (VLSI-DAT, 2014)

A New Methodology for Noise Sensor Placement Based on Association Rule Mining. - Yu-Hsiang Hung; Sheng-Hsin Fang; Hung-Ming Chen; Shen-Min Chen; Chang-Tzu Lin; Chia-Hsin Lee (ACM Great Lakes Symposium on VLSI, 2016)

Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. - Wei-Hsun Liao; Chang-Tzu Lin; Sheng-Hsin Fang; Chien-Chia Huang; Hung-Ming Chen; Ding-Ming Kwai; Yung-Fa Chou (ASP-DAC, 2017)

On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC. - Sheng-Hsin Fang; Chang-Tzu Lin; Wei-Hsun Liao; Chien-Chia Huang; Li-Chin Chen; Hung-Ming Chen; I-Hsuan Lee; Ding-Ming Kwai; Yung-Fa Chou (ISVLSI, 2017)

More Effective Power Network Prototyping by Analytical and Centroid Learning. - Yu-Hsiang Chuang; Chang-Tzu Lin; Hung-Ming Chen; Chi-Han Lee; Ting-Sheng Chen (ISCAS, 2019)

Learning Based Placement Refinement to Reduce DRC Short Violations. - Ying-Yao Huang; Chang-Tzu Lin; Wei-Lun Liang; Hung-Ming Chen (VLSI-DAT, 2021)

Practical Self-Supervised Model for Continual Learning. - Wen-Hwa Liao; Chang-Tzu Lin; Ssu-Chi Kuai (ICCE-Taiwan, 2024)