A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. - Min-Jae Seo; Dong-Hwan Jin; Ye-Dam Kim; Jong-Pal Kim; Dong-Jin Chang; Won-Mook Lim; Jae-Hyun Chung; Chang-Un Park; Eun-Ji An; Seung-Tak Ryu (A-SSCC, 2019)

An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC. - Jae-Hyun Chung; Ye-Dam Kim; Chang-Un Park; Kun-Woo Park; Min-Jae Seo; Seung-Tak Ryu (CICC, 2023)

A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration. - Chang-Un Park; Jae-Hyun Chung; Seung-Tak Ryu (CICC, 2023)

A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA. - Bo Gao; Lizhen Zhang; Raymond Mabilangan; Chang-Un Park; Kent Edrian Lozada; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (A-SSCC, 2024)

A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF. - Ye-Dam Kim; Jae-Hyun Chung; Kent Edrian Lozada; Chang-Un Park; Kun-Woo Park; Kwan-Hoon Song; Young-Hun Moon; Min-Jae Seo; Seung-Tak Ryu (VLSI Technology and Circuits, 2024)

A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC. - Jae-Hyun Chung; Ye-Dam Kim; Chang-Un Park; Kun-Woo Park; Dong-Ryeol Oh; Min-Jae Seo; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2024)