VEAP: Global optimization based efficient algorithm for VLSI placement. - Tianming Kong; Xianlong Hong; Changge Qiao (ASP-DAC, 1997)

A Timing-Driven Block Placer Based on Sequence Pair Model. - Gang Huang; Xianlong Hong; Changge Qiao; Yici Cai (ASP-DAC, 1999)

Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells. - Xiaohai Wu; Changge Qiao; Xianlong Hong (ASP-DAC, 1999)

Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction. - Hongyu Chen 001; Changge Qiao; Feng Zhou; Chung-Kuan Cheng (SLIP, 2002)

On improving optimization effectiveness in interconnect-driven physical synthesis. - Prashant Saxena; Vishal Khandelwal; Changge Qiao; Pei-Hsin Ho; J.-C. Lin; Mahesh A. Iyer (ISPD, 2009)