Short-Range, Wireless Interconnect within a Computing Chassis: Design Challenges. - Patrick Yin Chiang; Sirikarn Woracheewan; Changhui Hu 003; Lei Guo; Rahul Khanna; Jay J. Nejedlo; Huaping Liu 002 (IEEE Des. Test Comput., 2010)

Chaotic Pulse-Position Baseband Modulation for an Ultra-Wideband Transceiver in CMOS. - Patrick Yin Chiang; Changhui Hu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

All-digital 3-50 GHz ultra-wideband pulse generator for short-range wireless interconnect in 40nm CMOS. - Changhui Hu 003; Patrick Yin Chiang (CICC, 2011)

A 90 nm-CMOS, 500 Mbps, 3-5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization. - Changhui Hu 003; Rahul Khanna; Jay J. Nejedlo; Kangmin Hu; Huaping Liu 002; Patrick Yin Chiang (IEEE J. Solid State Circuits, 2011)

A Near-Threshold, 0.16 nJ/b OOK-Transmitter With 0.18 nJ/b Noise-Cancelling Super-Regenerative Receiver for the Medical Implant Communications Service. - Chao Ma 020; Changhui Hu 003; Jiao Cheng; Lingli Xia; Patrick Yin Chiang (IEEE Trans. Biomed. Circuits Syst., 2013)

20.5 A 40nm dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s over-the-air throughput. - Ming He; Renaldi Winoto; Xiang Gao; Wayne Loeb; David Signoff; Wai Lau; Yuan Lu; Donghong Cui; Kun-Seok Lee; Sai-Wang Tam; Philip Godoy; Yung Chen; et al. (ISSCC, 2014)