A 1.5-GS/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS. - Eunsang Lee; Changhyun Pyo; Sanghun Lee; Jaeduk Han (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

WITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth Memory. - Seoyoon Jang; Sangouk Jeon; Kwanghyun Shin; Dongkwon Lee; Hankyu Chi; Wookjin Shin; Changhyun Pyo; Jaeha Kim; Dongsuk Jeon (ASP-DAC, 2025)

22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces. - Boram Kim; Hankyu Chi; Hyeongjun Ko; Sang-Yeon Byeon; Sungkwon Lee; Changhyun Pyo; Seulgi Kim; Byungjun Kang; Eunji Song; Kwangjin Na; Jin-Youp Cha; Hyesoo Kim; et al. (ISSCC, 2025)