A 4-nm 9.6-Gb/s/pin LPDDR5X PHY With Adaptive Driver Strength Control and Fast Periodic Training for Full DVFS DRAM. - Yoonjae Choi; Jaegeun Song; Daero Kim; Myunggon Kim; Jiyeon Park; Jinho Choi; Changki Kwon; Minho Seo; Jihun Oh; Shinyoung Yi 002; Billy Koo; Kwanyeob Chae; et al. (A-SSCC, 2024)