Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor. - Yifan YangGong; Sebastian Turullols; Daniel Woo; Changku Huang; King C. Yen; Venkatram Krishnaswamy; Kalon Holdbrook; Jinuk Luke Shin (A-SSCC, 2014)