On-Chip IDDQ testability schemes for detecting multiple faults in CMOS ICs. - Changku Hwang; Mohammed Ismail 001; Joanne DeGroat (IEEE J. Solid State Circuits, 1996)

A 40nm 16-core 128-thread CMT SPARC SoC processor. - Jinuk Luke Shin; Kenway W. Tam; Dawei Huang; Bruce Petrick; Ha Pham; Changku Hwang; Hongping Penny Li; Alan P. Smith 002; Timothy Johnson; Francis Schumacher; David Greenhill; Ana Sonia Leon; et al. (ISSCC, 2010)

A 40 nm 16-Core 128-Thread SPARC SoC Processor. - Jinuk Luke Shin; Dawei Huang; Bruce Petrick; Changku Hwang; Kenway W. Tam; Alan P. Smith 002; Ha Pham; Hongping Penny Li; Timothy Johnson; Francis Schumacher; Ana Sonia Leon; Allan Strong (IEEE J. Solid State Circuits, 2011)

3.6GHz 16-core SPARC SoC processor in 28nm. - Jason Hart; Steve Butler; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Timothy Johnson; Georgios K. Konstadinidis; Lance Kwong; Robert P. Masleid; et al. (ISSCC, 2013)

A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm. - Jason Hart; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Timothy Johnson; Georgios K. Konstadinidis; Venkatram Krishnaswamy; Lance Kwong; Robert P. Masleid; et al. (IEEE J. Solid State Circuits, 2014)

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. - Penny Li; Jinuk Luke Shin; Georgios K. Konstadinidis; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; et al. (ISSCC, 2015)

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. - Georgios K. Konstadinidis; Hongping Penny Li; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; Vijay Srinivasan; et al. (IEEE J. Solid State Circuits, 2016)