12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. - Taejoong Song; Hoonki Kim; Woojin Rim; Yongho Kim; Sunghyun Park 003; Changnam Park; Minsun Hong; Giyong Yang; Jeongho Do; Jinyoung Lim; Seungyoung Lee; Ingyum Kim; et al. (ISSCC, 2017)

A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications. - Taejoong Song; Jonghoon Jung; Woojin Rim; Hoonki Kim; Yongho Kim; Changnam Park; Jeongho Do; Sunghyun Park 003; Sungwee Cho; Hyuntaek Jung; Bongjae Kwon; Hyun-Su Choi; et al. (ISSCC, 2018)

Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. - Woong Choi; Jongsun Park 001; Hoonki Kim; Changnam Park; Taejoong Song (VLSI Circuits, 2018)

A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology. - Inhak Lee; Hanwool Jeong; Sangyeop Baeck; Siddharth Gupta 008; Changnam Park; Dongwook Seo; Jaeseung Choi 001; Jaeyoung Kim; Hoon Kim; Jungmyung Kang; Sunyung Jang; Daeyoung Moon; et al. (ISSCC, 2019)

Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{ mathrm{MIN}}$ Improvement and Energy Saving. - Hanwool Jeong; Se Hyeok Oh; Tae Woo Oh; Hoonki Kim; Changnam Park; Woojin Rim; Taejoong Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2019)

A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation. - Hanwool Jeong; Tae Hyun Kim; Changnam Park; Hoonki Kim; Taejoong Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2021)

A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit. - Taejoong Song; Hoonki Kim; Woojin Rim; Hakchul Jung; Changnam Park; Inhak Lee; Sanghoon Baek; Jonghoon Jung (IEEE J. Solid State Circuits, 2022)