A static power saving TTL-to-CMOS input buffer. - Changsik Yoo; Min-Kyu Kim; Wonchan Kim (IEEE J. Solid State Circuits, 1995)

A ±1.5V 4MHz Low-Pass Gm-C Filter in CMOS. - Changsik Yoo; Wonchan Kim (ASP-DAC, 1998)

A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning. - Changsik Yoo; Seung-Wook Lee; Wonchan Kim (IEEE J. Solid State Circuits, 1998)

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM. - Hongil Yoon; Gi-Won Cha; Changsik Yoo; Nam-Jong Kim; Keum-Yong Kim; Chang Ho Lee; Kyu-Nam Lim; Kyuchan Lee; Jun-Young Jeon; Tae Sung Jung; Hongsik Jeong; Tae-Young Chung; et al. (IEEE J. Solid State Circuits, 1999)

A process and environment tolerant 3V, 2 GHz VCO with 0.8 μm CMOS technology. - Keewook Jung; Changsik Yoo; Hyun-Kyu Yu; Wonchui Song; Wonchan Kim (IEEE Trans. Consumer Electron., 1999)

A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25-μm CMOS. - Changsik Yoo; Qiuting Huang (IEEE J. Solid State Circuits, 2001)

A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention. - Sungkyung Park 003; Changsik Yoo; Sin-Chong Park (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM. - Chun-Seok Jeong; Changsik Yoo; Jae-Jin Lee; Joongsik Kih (ESSCIRC, 2004)

A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration. - Changsik Yoo; Kye-Hyun Kyung; Kyunam Lim; Hi-Choon Lee; Joon-Wan Chai; Nak-Won Heo; Dong-Jin Lee; Chang-Hyun Kim (IEEE J. Solid State Circuits, 2004)

A 1.2V, 10MHz, low-pass Gm-C filter with Gm-cells based on triode-biased MOS and passive resistor in 0.13μm CMOS technology. - Jun-Gi Jo; Changsik Yoo; Chun-Seok Jeong; Chan-Young Jeong; Mi-Young Lee; Jong-Kee Kwon (CICC, 2005)

Active-RC channel selection filter tunable from 6 kHz to 18 MHz for software-defined radio. - Jin-Hong Hwang; Mi-Young Lee; Chan-Young Jeong; Changsik Yoo (ISCAS (5), 2005)

A low-ripple poly-Si TFT charge pump for driver-integrated LCD panel. - Changsik Yoo; Kyun-Lyeol Lee (IEEE Trans. Consumer Electron., 2005)

Display System Interface without Line Memory for Low-Cost System-on-Glass. - Kyungyoul Min; Changsik Yoo (IEEE Trans. Consumer Electron., 2007)

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-μm CMOS Technology. - Young-Suk Seo; Jang-Woo Lee; Hong-Jung Kim; Changsik Yoo; Jae-Jin Lee; Chun-Seok Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 2×2 MIMO tri-band dual-mode CMOS transceiver for worldwide WiMAX/WLAN applications. - Kyoohyun Lim; Sunki Min; Sanghoon Lee; Jaewoo Park; Kisub Kang; Hwahyeong Shin; Hyunchul Shim; Sechang Oh; Sungho Kim; Jong-Ryul Lee; Changsik Yoo; Kukjin Chun (ESSCIRC, 2010)

A 0.6 V, 2.11 MHz, 62 dB SFDR active-RC filter in 0.13µm CMOS process. - Ji-Hwan Seok; Jun-Gi Jo; Changsik Yoo (Int. J. Circuit Theory Appl., 2010)

Spread spectrum clock generation for reduced electro-magnetic interference in consumer electronics devices. - Jang-Woo Lee; Hong-Jung Kim; Changsik Yoo (IEEE Trans. Consumer Electron., 2010)

A 1.62/2.7Gbps clock and data recovery with pattern based frequency detector for displayport. - Kyungyoul Min; Changsik Yoo (IEEE Trans. Consumer Electron., 2010)

A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DWA. - Jun-Gi Jo; Jinho Noh; Changsik Yoo (IEEE J. Solid State Circuits, 2011)

A 2x2 MIMO Tri-Band Dual-Mode Direct-Conversion CMOS Transceiver for Worldwide WiMAX/WLAN Applications. - Kyoohyun Lim; Sunki Min; Sang-Hoon Lee; Jaewoo Park; Kisub Kang; Hwahyeong Shin; Hyunchul Shim; Sechang Oh; Sungho Kim; Jong-Ryul Lee; Changsik Yoo; Kukjin Chun (IEEE J. Solid State Circuits, 2011)

Measurement of Intersymbol Interference Jitter by Fractional Oversampling for Adaptive Equalization. - Jang-Woo Lee; Chang-Hyun Bae; Younghoon Kim; Changsik Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Load-Independent Current Control Technique of a Single-Inductor Multiple-Output Switching DC-DC converter. - Young-Jin Moon; Yong-Seong Roh; Jung-Chul Gong; Changsik Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Class-D Amplifier With Pulse Code Modulated (PCM) Digital Input for Digital Hearing Aid. - Jinho Noh; Dongjun Lee; Jun-Gi Jo; Changsik Yoo (IEEE J. Solid State Circuits, 2013)

Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface. - Jang-Woo Lee; Hong-Jung Kim; Chun-Seok Jeong; Jae-Jin Lee; Changsik Yoo (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Digital phase locked loop (DPLL) with offset dithered bang-bang phase detector (BBPD) for bandwidth control. - Younghoon Kim; Min-Ki Jeon; Changsik Yoo (ISIC, 2014)

Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples. - Chang-Hyun Bae; Changsik Yoo (IEICE Electron. Express, 2014)

A 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop. - Dong-Ho Choi; Changsik Yoo (IEICE Electron. Express, 2014)

A fast automatic frequency calibration technique for a 2-6 GHz frequency synthesizer. - Chan-Young Jeong; Dong-Ho Choi; Changsik Yoo (Int. J. Circuit Theory Appl., 2014)

A 100-kS/s 8.3-ENOB 1.7- µW Time-Domain Analog-to-Digital Converter. - Younghoon Kim; Changsik Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An analog sigma-delta modulator with shared operational amplifier for low-power class-D audio amplifier. - Jinho Noh; Jisoo Lee; Changsik Yoo (IEICE Electron. Express, 2015)

A 5.25-V-tolerant bidirectional I/O circuit in a 28-nm CMOS process. - Keun-Seon Ahn; Jaewoo Park; Changsik Yoo (Int. J. Circuit Theory Appl., 2015)

A 6-Gbps/lane receiver for a clock-forwarded link in 65-nm CMOS process. - Keun-Seon Ahn; Changsik Yoo (Int. J. Circuit Theory Appl., 2015)

Crosstalk cancelling voltage-mode driver for multi-Gbps parallel DRAM interface. - Younghoon Kim; Changsik Yoo (Int. J. Circuit Theory Appl., 2015)

A switch-mode boost DC-DC converter for IR-drop compensation of charging cable. - Young-Jin Moon; Changsik Yoo (Int. J. Circuit Theory Appl., 2015)

Variation-Tolerant Sensing Circuit for Spin-Transfer Torque MRAM. - Kyungmin Kim 003; Changsik Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A HDMI-to-MHL video format conversion system-on-chip (SoC) for mobile handset in a 130-nm CMOS technology. - Hyochang Kim; Jaewoo Park; Woosang Han; Kyuhwan Oh; Taekjun Ahn; Jun-Gi Jo; Ook Kim; Changsik Yoo (ICCE, 2016)

Wireless power charger for wearable medical devices with in-band communication. - Young-Jin Moon; Jeongpyo Park; Min-Gyu Jeong; Sang-Hyun Kim; Jin-Gyu Kang; Dong-Zo Kim; Changsik Yoo (Int. J. Circuit Theory Appl., 2016)

Quasi-Resonant (QR) Controller With Adaptive Switching Frequency Reduction Scheme for Flyback Converter. - Jeongpyo Park; Young-Jin Moon; Min-Gyu Jeong; Jin-Gyu Kang; Sang-Hyun Kim; Jung-Chul Gong; Changsik Yoo (IEEE Trans. Ind. Electron., 2016)

A Stochastic Flash Analog-to-Digital Converter Linearized by Reference Swapping. - Min-Ki Jeon; Won-Jun Yoo; Chan-Gyu Kim; Changsik Yoo (IEEE Access, 2017)

Duty-cycle and phase spacing error correction circuit for high-speed serial link. - Hyochang Kim; Ook Kim; Changsik Yoo (IEICE Electron. Express, 2017)

A simultaneously bidirectional inductively coupled link in a 0.13-µm CMOS technology. - Min-Ki Jeon; Changsik Yoo (Int. J. Circuit Theory Appl., 2017)

A 10MHz time-domain-controlled current-mode buck converter with 8.5% to 93% switching duty cycle. - Jin-Gyu Kang; Min-Gyu Jeong; Jeongpyo Park; Changsik Yoo (ISSCC, 2018)

Continuous-time linear equalizer with automatic boosting gain adaptation and input offset cancellation. - Baek-Jin Lim; Changsik Yoo (Int. J. Circuit Theory Appl., 2018)

Time-Based Digital LDO Regualtor with Fractionally Controlled Power Transistor Strength and Fast Transient Response. - Jin-Gyu Kang; Min-Gyu Jeong; Jeongpyo Park; Changsik Yoo (A-SSCC, 2019)

A Time-Domain-Controlled Current-Mode Buck Converter With Wide Output Voltage Range. - Jin-Gyu Kang; Jeongpyo Park; Min-Gyu Jeong; Changsik Yoo (IEEE J. Solid State Circuits, 2019)

A 4-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Stochastic Quantizer and Digital Accumulator. - Donghyeok Jeong; Changsik Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Current-Mode Hysteretic Buck Converter With Multiple-Reset RC-Based Inductor Current Sensor. - Min-Gyu Jeong; Jin-Gyu Kang; Jeongpyo Park; Changsik Yoo (IEEE Trans. Ind. Electron., 2019)

Time-Domain Operational Amplifier With Voltage-Controlled Oscillator and Its Application to Active-RC Analog Filter. - Kyungmin Kim 003; Changsik Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS. - Hyochang Kim; Changsik Yoo (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. - Hojun Yoon; Wonjoo Jung; Jaewoo Park; Jindo Byun; Hyungmin Jin; Hyunyoon Cho; Youngmin Kim; Baek-Jin Lim; Young-Chul Cho; Youngdon Choi; Jung-Hwan Choi; Hyungjong Ko; et al. (ESSCIRC, 2021)

A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM. - Seunghwan Hong; Chang-Hyun Bae; Yoo-Chang Sung; Jaewoong Kim; Junsub Yoon; Sangwoo Kim; Jin-Hyeok Baek; Cheongryong Cho; Useung Shin; Sang-Kyeom Kim; Hwan-Chul Jung; Ho-Jun Chang; et al. (VLSI Circuits, 2021)

Solar Energy-Harvesting Buck-Boost Converter With Battery-Charging and Battery-Assisted Modes. - Jeongpyo Park; Min-Gyu Jeong; Jin-Gyu Kang; Changsik Yoo (IEEE Trans. Ind. Electron., 2021)

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process. - Dae-Hyun Kim 003; Byungkyu Song; Hyun-A. Ahn; Woongjoon Ko; Sung-Geun Do; Seokjin Cho; Kihan Kim; Seung-Hoon Oh; Hye-Yoon Joo; Geuntae Park; Jin-Hun Jang; Yong-Hun Kim; et al. (ISSCC, 2022)

A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. - Hyun-A. Ahn; Yoo-Chang Sung; Yong-Hun Kim; Janghoo Kim; Kihan Kim; Donghun Lee; Young-Gil Go; Jae-Woo Lee; Jae-Woo Jung; Yong-Hyun Kim; Garam Choi; Jun-Seo Park; et al. (A-SSCC, 2023)

A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. - Jinook Jung; Jun-Han Choi; Kyoung-Jun Roh; Jaewoo Park; Won-Mook Lim; Tae-Sung Kim; Han-Ki Jeong; Myoungbo Kwak; Jaeyoun Youn; Jeong-Don Ihm; Changsik Yoo; Youngdon Choi; et al. (A-SSCC, 2023)

A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL. - Daehyun Kwon; Heon Su Jeong; Jaemin Choi; Wijong Kim; Jae Woong Kim; Junsub Yoon; Jungmin Choi; Sanguk Lee; Hyunsub Norbert Rie; Jin-Il Lee; Jongbum Lee; Taeseong Jang; et al. (ISSCC, 2023)

DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm. - Seungki Hong; Dongha Kim; Jaehyung Lee; Reum Oh; Changsik Yoo; Sang Joon Hwang; Jooyoung Lee (CoRR, 2023)

A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend. - Hyeongmin Seo; Jiyun Han; Kyungmin Kim 003; Baek-Jin Lim; EunSeok Shin; Youngdon Choi; Hyungjong Ko; Jung-Hwan Choi; Sang-Hyun Lee; Changsik Yoo; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS. - Hyuntae Kim; Hyeongmin Seo; Yunseong Jo; Changsik Yoo; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS. - Hyochang Kim; Hyeongmin Seo; Hyuntae Kim; Changsik Yoo; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier with Ground Precharge and Charge Transfer Pre sensing for Sub-1V DRAM. - Changyoung Lee; Youngseok Park; Hyunchul Yoon; Seryeong Yoon; Donggeon Kim; Bokyeon Won; Junhwa Song; In-Jae Bae; Jaejoon Song; Kyuchang Kang; Jaehyuk Kim; Kyungrak Cho; et al. (A-SSCC, 2024)

13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sanghoon Kim; Daewoong Lee; Seongyeal Yang; Gil-Young Kang; Juseop Park; Kyungho Lee; Hwan-Chul Jung; Gun-hee Cho; et al. (ISSCC, 2024)

An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM. - Kyeongtae Nam; Jaehyuk Kim; Dongil Lee; Kyuchang Kang; Sangyun Kim; Changyoung Lee; Hyunchul Yoon; Donggeon Kim; Bokyeon Won; Jaejoon Song; Incheol Nam; Young-Hun Seo; et al. (VLSI Technology and Circuits, 2024)

A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. - Jinook Jung; Jun-Han Choi; Kyoung-Jun Roh; Jaewoo Park; Won-Mook Lim; Tae-Sung Kim; Han-Ki Jeong; Myoungbo Kwak; Jaeyoun Youn; Jeong-Don Ihm; Changsik Yoo; Youngdon Choi; et al. (IEEE J. Solid State Circuits, 2024)

Improvement of IGZO BTI for DRAM Cell application by heat treatment and recovery effect. - Changsik Kim; Jongmoo Lee; Jihee Jun; Chanhee Han; In-Jae Bae; Youngkwan Park; Hana Cho; Hyeontae Kim; Dongsik Park; Heonjun Ha; Jaejoon Song; Changsik Yoo; et al. (IRPS, 2025)

A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sang-Hoon Kim; Daewoong Lee; Seongyeal Yang; Se-Mi Kim; Gil-Young Kang; Juseop Park; Kyung-Ho Lee; Hwan-Chul Jung; et al. (IEEE J. Solid State Circuits, 2025)

An Offset Compensated Charge Transfer Pre-Sensing Bitline Sense Amplifier. - Kyeongtae Nam; Dongil Lee; Kyuchang Kang; Sangyun Kim; Changyoung Lee; Hyunchul Yoon; Donggeon Kim; Bokyeon Won; Jaejoon Song; Jaehyuk Kim; Incheol Nam; Young-Hun Seo; et al. (IEEE J. Solid State Circuits, 2025)