A 185 μW -105.1 dB THD 88.6 dB SNDR Negative-R Stabilized Audio Preamplifier. - Seung-Woo Song; Changuk Lee; Moon Hyung Jang; Youngcheol Chae (ESSCIRC, 2019)

Analysis and Design of Low-Power Continuous-Time Delta-Sigma Modulator Using Negative-R Assisted Integrator. - Moon Hyung Jang; Changuk Lee; Youngcheol Chae (IEEE J. Solid State Circuits, 2019)

Design Considerations for External Compensation Approaches to OLED Display Degradation. - Jaewook Kwon; Changuk Lee; Youngcheol Chae; Boris Murmann (ISCAS, 2020)

9.2 A 134µW 24kHz-BW 103.5d8-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC. - Moon Hyung Jang; Changuk Lee; Youngcheol Chae (ISSCC, 2020)

23.8 A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation. - Yunhong Kim; Sungsik Park; Seung-Woo Song; Sangwoo Lee; Moon Hyung Jang; Changuk Lee; Youngcheol Chae (ISSCC, 2020)

26.6 A 6.5µW 10kHz-BW 80.4dB-SNDR Continuous-Time ΔΣ Modulator with Gm-Input and 300mVpp Linear Input Range for Closed-Loop Neural Recording. - Changuk Lee; Taejune Jeon; Moon Hyung Jang; Sanggeon Park; Yeowool Huh; Youngcheol Chae (ISSCC, 2020)

A 6.5-μW 10-kHz BW 80.4-dB SNDR Gm-C-Based CT ∆∑ Modulator With a Feedback-Assisted Gm Linearization for Artifact-Tolerant Neural Recording. - Changuk Lee; Taejune Jeon; Moon Hyung Jang; Sanggeon Park; Jejung Kim; Jeongsik Lim; Jong-Hyun Ahn; Yeowool Huh; Youngcheol Chae (IEEE J. Solid State Circuits, 2020)

A 0.033-mm2 21.5-aF Resolution Continuous-Time Delta-Sigma Capacitance-to-Digital Converter with Parasitic Capacitance Immunity up to 480pF. - Hyeyeon Lee; Changuk Lee; Jae-Youl Lee; Yoon-Kyung Choi; Youngcheol Chae (A-SSCC, 2021)

A Negative R-Assisted Amplifier on the Virtual Ground and Its Applications. - Youngcheol Chae; Moon Hyung Jang; Changuk Lee; Sangwoo Lee; Seung-Woo Song (CICC, 2021)

A 47.5nJ Resistor-to-Digital Converter for Detecting BTEX with 0.06ppb-Resolution. - Yongtae Lee; Byeonghwa Cho; Changuk Lee; Jongbaeg Kim; Youngcheol Chae (VLSI Circuits, 2021)

A 134-μW 99.4-dB SNDR Audio Continuous-Time Delta-Sigma Modulator With Chopped Negative-R and Tri-Level FIR-DAC. - Moon Hyung Jang; Changuk Lee; Youngcheol Chae (IEEE J. Solid State Circuits, 2021)

A Miniaturized Wireless Neural Implant with Body-Coupled Data Transmission and Power Delivery for Freely Behaving Animals. - Changuk Lee; Byeongseol Kim; Jejung Kim; Sangwon Lee; Taejune Jeon; Woojun Choi; Sunggu Yang; Jong-Hyun Ahn; Joonsung Bae; Youngcheol Chae (ISSCC, 2022)

A Miniaturized Wireless Neural Implant With Body-Coupled Power Delivery and Data Transmission. - Changuk Lee; Byeongseol Kim; Jejung Kim; Sangwon Lee; Taejune Jeon; Woojun Choi; Sunggu Yang; Jong-Hyun Ahn; Joonsung Bae; Youngcheol Chae (IEEE J. Solid State Circuits, 2022)

A 0.033-mm2 21.5-aF to 114.9-aF Resolution Continuous-Time Δ Σ Capacitance-to-Digital Converter Achieving Parasitic Capacitance Immunity Up to 480 pF. - Hyeyeon Lee; Changuk Lee; Inhee Lee 001; Youngcheol Chae (IEEE J. Solid State Circuits, 2022)

An 11bit 360MS/s Pipelined SAR ADC with Dynamic Negative-C Assisted Residue Amplifier. - Yigi Kwon; Sangwoo Lee; Changuk Lee; Hyunchul Yoon; Byounghan Min; Youngcheol Chae (A-SSCC, 2023)

A 243μW 97.4dB-DR 50kHz-BW Multi-Rate CT Zoom ADC with Inherent DAC Mismatch Tolerance. - Junghyun Yoon; Moon Hyung Jang; Changuk Lee; Yong Lim; Youngcheol Chae (CICC, 2023)

A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces. - Moon Hyung Jang; Wei-Han Yu; Changuk Lee; Maddy Hays; Pingyu Wang; Nick Vitale; Pulkit Tandon; Pumiao Yan; Pui-In Mak; Youngcheol Chae; E. J. Chichilnisky; Boris Murmann; et al. (VLSI Technology and Circuits, 2023)

A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier. - Hyunchul Yoon; Changuk Lee; Taewoong Kim; Yigi Kwon; Youngcheol Chae (IEEE J. Solid State Circuits, 2023)

A 0.5-ms 47.5-nJ Resistor-to-Digital Converter for Resistive BTEX Sensor Achieving 0.1-to-5 ppb Resolution. - Yongtae Lee; Byeonghwa Cho; Changuk Lee; Jongbaeg Kim; Youngcheol Chae (IEEE J. Solid State Circuits, 2023)

A Wireless Neurostimulator Using Body-Coupled Link for Multisite Stimulation in Freely Behaving Animals. - Taejune Jeon; Byeongseol Kim; Changuk Lee; Danbi Ahn; Daerl Park; Jaesuk Sung; Hee Young Kim; Heonjin Choi; Joonsung Bae; Youngcheol Chae (VLSI Technology and Circuits, 2024)

A 1024-Channel 268-nW/Pixel 36×36 μm2/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces. - Moon Hyung Jang; Maddy Hays; Wei-Han Yu; Changuk Lee; Pietro Caragiulo; Athanasios T. Ramkaj; Pingyu Wang; A. J. Phillips; Nick Vitale; Pulkit Tandon; Pumiao Yan; Pui-In Mak; et al. (IEEE J. Solid State Circuits, 2024)

35.8 DustNet: A Network of Time-Division Multiplexed Ultrasonic Implants with 16-Level ASK Backscatter Modulation. - Changuk Lee; Jade Pinkenburg; Mohammad Meraj Ghanbari; Cem Yalcin; Miguel Montalban; Rikky Muller (ISSCC, 2025)

An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth. - Junghyun Yoon; Moon Hyung Jang; Changuk Lee; Yong Lim; Youngcheol Chae (IEEE J. Solid State Circuits, 2025)