A 3.8-dB NF, 23-40GHz Phased-Array Receiver with 14-Bit Phase & Gain Manager and Calibration-Free Dual-Mode 28-52dB Image Rejection Ratio for 5G NR. - Zhixian Deng; Huizhen Jenny Qian; Changxuan Han; Yifan Li; Xun Luo (CICC, 2022)

A 71-to-86GHz, 20.4dBm $ mathbf{P}_{ mathbf{out}}$, 6.0dB NF Transceiver with Quadrature Direct-Modulated Transmitter and Reflection-Less Heterodyne Receiver in 40nm CMOS. - Jie Zhou 026; Changxuan Han; Wen Chen; Bingzheng Yang; Xun Luo (A-SSCC, 2023)

An 8-Element 23-40 GHz Continuously Auto Link-Tracking Phased-Array Transceiver with Time Division Modulator Achieving 7μs Tracking Time, 25.3% TX System Efficiency, 800MHz-64QAM Modulation for 5G NR. - Zhixian Deng; Bingzheng Yang; Wen Chen; Jie Zhou 026; Changxuan Han; Yifan Li; Yiyang Shu; Xun Luo (CICC, 2023)

A 4.8dB NF, 70-to-86GHz Deep-Noise-Canceling LNA Using Asymmetric Compensation Transformer and 4-to-1 Hybrid-Phase Combiner in 40nm CMOS. - Changxuan Han; Jie Zhou 026; Zhixian Deng; Yiyang Shu; Xun Luo (ISSCC, 2023)

A 23-40-GHz Phased-Array Receiver Using 14-Bit Phase-Gain Manager and Wideband Noise-Canceling LNA. - Zhixian Deng; Changxuan Han; Yifan Li; Huizhen Jenny Qian; Xun Luo (IEEE J. Solid State Circuits, 2023)

A -10.1dBm IIP3, 0.3-40GHz Receiver Using Hybrid-Path Band-Selection with Reduced LO Coverage Bandwidth Supporting 480Mb/s 4096-QAM and 7.2Gb/s 64-QAM Modulation. - Changxuan Han; Xun Luo (CICC, 2024)

A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation. - Changxuan Han; Zhixian Deng; Yiyang Shu; Jun Yin 001; Pui-In Mak; Xun Luo (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 70-86-GHz Deep-Noise-Canceling LNA With Dual-Stage Noise Cancellation Using Asymmetric Compensation Transformer and 4-to-1 Hybrid-Phase Combiner. - Changxuan Han; Jie Zhou 026; Xun Luo (IEEE J. Solid State Circuits, 2025)