A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end. - Xuan Wang; Changyi Yang; Xiaoxiao Zhao; Chao Wu; Fule Li; Zhihua Wang 001; Bin Wu (ISCAS, 2012)

A merged first and second stage for low power pipelined ADC. - Changyi Yang; Weitao Li; Fule Li; Zhihua Wang 001 (ISCAS, 2013)

A power-efficient reference buffer with wide swing for switched-capacitor ADC. - Weitao Li; Fule Li; Changyi Yang; Minzeng Li; Zhihua Wang 001 (Microelectron. J., 2015)