17.1 A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction. - Yongsun Lee; Taeho Seong; Jeonghyun Lee; Chanwoong Hwang; Hangi Park; Jaehyouk Choi (ISSCC, 2020)

17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word. - Taeho Seong; Yongsun Lee; Chanwoong Hwang; Jeonghyun Lee; Hangi Park; Kyuho Jason Lee; Jaehyouk Choi (ISSCC, 2020)

Semi-supervised based Unknown Attack Detection in EDR Environment. - Chanwoong Hwang; Doyeon Kim; Taejin Lee 002 (KSII Trans. Internet Inf. Syst., 2020)

A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM. - Hangi Park; Chanwoong Hwang; Taeho Seong; Yongsun Lee; Jaehyouk Choi (ISSCC, 2021)

An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS. - Seyeon Yoo; Suneui Park; Seojin Choi; Yoonseo Cho; Heein Yoon; Chanwoong Hwang; Jaehyouk Choi (ISSCC, 2021)

Research on Improvement of Anomaly Detection Performance in Industrial Control Systems. - Sungho Bae; Chanwoong Hwang; Taejin Lee 002 (WISA, 2021)

E-SFD: Explainable Sensor Fault Detection in the ICS Anomaly Detection System. - Chanwoong Hwang; Taejin Lee 002 (IEEE Access, 2021)

A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. - Chanwoong Hwang; Hangi Park; Taeho Seong; Jaehyouk Choi (ISSCC, 2022)

A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM. - Chanwoong Hwang; Hangi Park; Yongsun Lee; Taeho Seong; Jaehyouk Choi (IEEE J. Solid State Circuits, 2022)

A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. - Hangi Park; Chanwoong Hwang; Taeho Seong; Jaehyouk Choi (IEEE J. Solid State Circuits, 2022)

A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier. - Yongwoo Jo; Juyeop Kim; Yuhwan Shin; Chanwoong Hwang; Hangi Park; Jaehyouk Choi (ISSCC, 2023)

A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier. - Yongwoo Jo; Juyeop Kim; Yuhwan Shin; Hangi Park; Chanwoong Hwang; Younghyun Lim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2023)

10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm. - Seheon Jang; Munjae Chae; Hangi Park; Chanwoong Hwang; Jaehyouk Choi (ISSCC, 2024)

A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm. - Seheon Jang; Munjae Chae; Hangi Park; Chanwoong Hwang; Jaehyouk Choi (IEEE J. Solid State Circuits, 2024)

34.1 A 65fsrms-Jitter and -272dB-FoMjitter, N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration. - Munjae Chae; Seheon Jang; Chanwoong Hwang; Hangi Park; Jaehyouk Choi (ISSCC, 2025)