A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process. - Wei-Bin Yang; Chao-Cheng Liao; Yung-Chih Liang (Microelectron. J., 2011)

A multiple frequency clock generator using wide operation frequency range phase interpolator. - Wei-Bin Yang; Chi-Hsiung Wang; Sheng-Shih Yeh; Chao-Cheng Liao (Microelectron. J., 2013)