14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S. - Tsung-Hsien Tsai; Min-Shueh Yuan; Chih-Hsien Chang; Chia-Chun Liao; Chao-Chieh Li; Robert Bogdan Staszewski (ISSCC, 2015)

A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. - Chao-Chieh Li; Tsung-Hsien Tsai; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo; Kenny Hsieh; Mark Chen 001; Augusto Ronchini Ximenes; et al. (VLSI Circuits, 2016)

19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications. - Chao-Chieh Li; Min-Shueh Yuan; Chih-Hsien Chang; Yu-Tso Lin; Chia-Chun Liao; Kenny Hsieh; Mark Chen 001; Robert Bogdan Staszewski (ISSCC, 2017)

A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference. - Min-Shueh Yuan; Chao-Chieh Li; Chia-Chun Liao; Yu-Tso Lin; Chih-Hsien Chang; Robert Bogdan Staszewski (ISSCC, 2018)

All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply. - Chao-Chieh Li; Min-Shueh Yuan; Chia-Chun Liao; Yu-Tso Lin; Chih-Hsien Chang; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2018)

A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Tom Chen 002; Wen-Hung Huang; Jack Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (VLSI Circuits, 2019)

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Ching-Fang Chen; Wen-Hung Huang; Chi-Wei Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (IEEE J. Solid State Circuits, 2020)

A 0.2-V Three-Winding Transformer-Based DCO in 16-nm FinFET CMOS. - Chao-Chieh Li; Min-Shueh Yuan; Yu-Tso Lin; Chia-Chun Liao; Chih-Hsien Chang; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst., 2020)

A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS. - Chao-Chieh Li; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Yu-Tso Lin; Tsung-Hsien Tsai; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo; Augusto Ronchini Ximenes; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Tze-Chiang Huang; Wen-Hung Huang; Kate Huang; Yu-Chi Chen; Alex Liu; Yu-Jie Huang; Jimmy Wang; Shu-Chun Yang; Nai-Chen Cheng 001; et al. (VLSI Technology and Circuits, 2024)

36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Wei-Chih Chen; Wen-Hung Huang; Yu-Chi Chen; Yu-Jie Huang; Alan J. Drake; Chin-Hua Wen; Paul Ranucci; Hsin-Hung Kuo; Aidong Yin; et al. (ISSCC, 2025)