A leakage-suppression technique for phase-locked systems in 65nm CMOS. - Chao-Ching Hung; Shen-Iuan Liu (ISSCC, 2009)

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology. - Lan-Chou Cho; Chihun Lee; Chao-Ching Hung; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2009)

A Leakage-Compensated PLL in 65-nm CMOS Technology. - Chao-Ching Hung; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Noise Filtering Technique for Fractional-N Frequency Synthesizers. - Chao-Ching Hung; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm. - Chao-Ching Hung; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Toward Automotive Surround-View Radars. - Chih-Ming Hung; Alex T. C. Lin; B. C. Peng; Hua Wang; Jui-Lin Hsu; Yen-Ju Lu; Wei-Show Hsu; Jing-Hong Conan Zhan; Brian Juan; Chi-Hang Lok; Sam Lee; P. C. Hsiao; et al. (ISSCC, 2019)

19.3 A Fractional-N PLL with 34fsrms Jitter and -255.5dB FoM Based on a Multipath Feedback Technique. - Chao-Ching Hung; Chih-Hsien Shen; Chien-Li Lin; Mou Tzou; Kevin Fong; Yu-Li Hsueh (ISSCC, 2025)