A DLL-Based Variable-Phase Clock Buffer. - Chao-Chyun Chen; Jung-Yu Chang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line. - Chao-Chyun Chen; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2008)

A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithm. - Wei-Cheng Chen; Rong-Jyi Yang; Chia-Yu Yao; Chao-Chyun Chen (ISPACS, 2012)

A wide-range and fast-locking frequency synthesizer for Wimax and WLAN applications. - Chun-Yen Wu; Chi-Nan Chuang; Chao-Chyun Chen; I-Chyn Wey (GCCE, 2014)

A modified multi-fingers stru cture for power transistor in 0.16μm CMOS process. - Chao-Chyun Chen; Jiun-Wei Yang; Nai-Shen Kuo (ICCE-TW, 2014)

Design of VLSI Architecture of Autocorrelation-Based Lossless Recompression Engine for Memory-Efficient Video Coding Systems. - Yu-Hsuan Lee; Chao-Chyun Chen; Yi-Lun You (Circuits Syst. Signal Process., 2014)

A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM. - Wei-Cheng Chen; Chao-Chyun Chen; Chia-Yu Yao; Rong-Jyi Yang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

The Video Spatial Error Concealment Algorithm Using Separately-Directional Interpolation Technique. - Yu-Hsuan Lee; Cheng-Hung Lin; Chao-Chyun Chen; Shu-Yen Lin; Bo-Siang Huang (J. Signal Process. Syst., 2017)

Correction to: the Video Spatial Error Concealment Algorithm Using Separately-Directional Interpolation Technique. - Yu-Hsuan Lee; Cheng-Hung Lin; Chao-Chyun Chen; Shu-Yen Lin; Bo-Siang Huang (J. Signal Process. Syst., 2020)