A 2.5 Gbps CMOS optical receiver analog front-end. - Wei-Zen Chen; Chao-Hsin Lu (CICC, 2002)

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-μm digital CMOS technology. - Wei-Zen Chen; Chao-Hsin Lu (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS. - Yuan-Hung Chung; Min Chen; Wei-Kai Hong; Jie-Wei Lai; Sheng-Jau Wong; Chien-Wei Kuan; Hong-Lin Chu; Chihun Lee; Chih-Fan Liao; Hsuan-Yu Liu; Hong-Kai Hsu; Li-Chun Ko; et al. (ISSCC, 2012)

A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS. - Ying-Zu Lin; Chih-Hou Tsai; Shan-Chih Tsou; Chao-Hsin Lu (VLSI Circuits, 2016)

A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET. - Ying-Zu Lin; Chin-Yu Lin; Shan-Chih Tsou; Chih-Hou Tsai; Chao-Hsin Lu (ISSCC, 2019)

An 80MHz-BW 640MS/s Time-Interleaved Passive Noise- Shaping SAR ADC in 22nm FDSOI Process. - Chin-Yu Lin; Ying-Zu Lin; Chih-Hou Tsai; Chao-Hsin Lu (ISSCC, 2021)