A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists. - Chao-Kuei Chung; Chien-Yu Lu; Zhi-Hao Chang; Shyh-Jye Jou; Ching-Te Chuang; Ming-Hsien Tu; Yu-Hsian Chen; Yong-Jyun Hu; Paul-Sen Kan; Huan-Shun Huang; Kuen-Di Lee; Yung-Shin Kao (SoCC, 2014)