An Improved Polynomial-Time Algorithm for Designing Digital Filters with Power-of-Two Coefficients. - Chao-Liang Chen; Kei-Yong Khoo; Alan N. Willson Jr. (ISCAS, 1995)

A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking. - Kei-Yong Khoo; Chao-Liang Chen; Alan N. Willson Jr. (ISCAS (1), 1999)

A 6.25 mm2 2.4 GHz CMOS 802.11b Transceiver. - Yong-Hsiang Hsieh; Wei-Yi Hu; Wen-Kai Li; Shin-Ming Lin; Chao-Liang Chen; David J. Chen; Sao-Jie Chen (IEICE Trans. Electron., 2005)

An auto-I/Q calibrated CMOS transceiver for 802.11g. - Yong-Hsiang Hsieh; Wei-Yi Hu; Shin-Ming Lin; Chao-Liang Chen; Wen-Kai Li; Sao-Jie Chen; David J. Chen (IEEE J. Solid State Circuits, 2005)