Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method. - Po-Chih Tseng; Chao-Tsung Huang; Liang-Gee Chen (APCCAS (1), 2002)

Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method. - Chao-Tsung Huang; Po-Chih Tseng; Liang-Gee Chen (ISCAS (5), 2002)

VLSI implementation of shape-adaptive discrete wavelet transform. - Po-Chih Tseng; Chao-Tsung Huang; Liang-Gee Chen (VCIP, 2002)

Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank. - Chao-Tsung Huang; Po-Chih Tseng; Liang-Gee Chen (ICIP (2), 2003)

Memory analysis and architecture for two-dimensional discrete wavelet transform. - Chao-Tsung Huang; Po-Chih Tseng; Liang-Gee Chen (ICASSP (5), 2004)

B-spline factorization-based architecture for inverse discrete wavelet transform. - Chao-Tsung Huang; Po-Chih Tseng; Liang-Gee Chen (ISCAS (2), 2004)

Reconfigurable discrete cosine transform processor for object-based video signal processing. - Po-Chih Tseng; Chao-Tsung Huang; Liang-Gee Chen (ISCAS (2), 2004)

Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform. - Chao-Tsung Huang; Po-Chih Tseng; Liang-Gee Chen (IEEE Trans. Signal Process., 2004)

Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering [video coding applications]. - Chao-Tsung Huang; Ching-Yeh Chen; Yi-Hau Chen; Liang-Gee Chen (ICASSP (5), 2005)

System analysis of VLSI architecture for motion-compensated temporal filtering. - Ching-Yeh Chen; Chao-Tsung Huang; Yi-Hau Chen; Chung-Jr Lian; Liang-Gee Chen (ICIP (3), 2005)

Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC. - Tung-Chien Chen; Yu-Wen Huang; Chuan-Yung Tsai; Chao-Tsung Huang; Liang-Gee Chen (ISCAS (2), 2005)

Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT. - Chih-Chi Cheng; Chao-Tsung Huang; Po-Chih Tseng; Chia-Ho Pan; Liang-Gee Chen (ISCAS (5), 2005)

Advances in Hardware Architectures for Image and Video Coding - A Survey. - Po-Chih Tseng; Yung-Chi Chang; Yu-Wen Huang; Hung-Chi Fang; Chao-Tsung Huang; Liang-Gee Chen (Proc. IEEE, 2005)

Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method. - Chao-Tsung Huang; Po-Chih Tseng; Liang-Gee Chen (IEEE Trans. Circuits Syst. Video Technol., 2005)

Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform. - Chao-Tsung Huang; Po-Chih Tseng; Liang-Gee Chen (IEEE Trans. Signal Process., 2005)

VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters. - Chao-Tsung Huang; Po-Chih Tseng; Liang-Gee Chen (J. VLSI Signal Process., 2005)

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization. - Chao-Tsung Huang; Po-Chih Tseng; Liang-Gee Chen (J. VLSI Signal Process., 2005)

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems. - Po-Chih Tseng; Chao-Tsung Huang; Liang-Gee Chen (J. VLSI Signal Process., 2005)

Line Buffer Wordlength Analysis for Line-Based 2-D DWT. - Chih-Chi Cheng; Chao-Tsung Huang; Jing-Ying Chang; Liang-Gee Chen (ICASSP (3), 2006)

Level C+ data reuse scheme for motion estimation with corresponding coding orders. - Ching-Yeh Chen; Chao-Tsung Huang; Yi-Hau Chen; Liang-Gee Chen (IEEE Trans. Circuits Syst. Video Technol., 2006)

High-Performance JPEG 2000 Encoder With Rate-Distortion Optimization. - Hung-Chi Fang; Yu-Wei Chang; Tu-Chih Wang; Chao-Tsung Huang; Liang-Gee Chen (IEEE Trans. Multim., 2006)

System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering. - Ching-Yeh Chen; Chao-Tsung Huang; Yi-Hau Chen; Shao-Yi Chien; Liang-Gee Chen (IEEE Trans. Signal Process., 2006)

On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform. - Chih-Chi Cheng; Chao-Tsung Huang; Ching-Yeh Chen; Chung-Jr Lian; Liang-Gee Chen (IEEE Trans. Circuits Syst. Video Technol., 2007)

A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications. - Chao-Tsung Huang; Mehul Tikekar; Chiraag Juvekar; Vivienne Sze; Anantha P. Chandrakasan (ISSCC, 2013)

HEVC interpolation filter architecture for quad full HD decoding. - Chao-Tsung Huang; Chiraag Juvekar; Mehul Tikekar; Anantha P. Chandrakasan (VCIP, 2013)

Energy and area-efficient hardware implementation of HEVC inverse transform and dequantization. - Mehul Tikekar; Chao-Tsung Huang; Vivienne Sze; Anantha P. Chandrakasan (ICIP, 2014)

A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications. - Mehul Tikekar; Chao-Tsung Huang; Chiraag Juvekar; Vivienne Sze; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2014)

Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction Architecture for Quad Full HD Video Decoding. - Chao-Tsung Huang; Mehul Tikekar; Anantha P. Chandrakasan (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Decoder Hardware Architecture for HEVC. - Mehul Tikekar; Chao-Tsung Huang; Chiraag Juvekar; Vivienne Sze; Anantha P. Chandrakasan (High Efficiency Video Coding, 2014)

Fast realistic refocusing for sparse light fields. - Chao-Tsung Huang; Jui Chin; Hong-Hui Chen; Yu-Wen Wang; Liang-Gee Chen (ICASSP, 2015)

Sub-pixel disparity estimation in continuous space. - Li-De Chen; Jo-Jiun Yu; Wei-Han Cheng; Chao-Tsung Huang (ICCE-TW, 2015)

23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications. - Hong-Hui Chen; Chao-Tsung Huang; Sih-Sian Wu; Chia-Liang Hung; Tsung-Chuan Ma; Liang-Gee Chen (ISSCC, 2015)

Bayesian Inference for Neighborhood Filters With Application in Denoising. - Chao-Tsung Huang (IEEE Trans. Image Process., 2015)

VLSI architecture design of weighted mode filter for Full-HD depth map upsampling at 30fps. - Li-De Chen; Yu-Ling Hsiao; Chao-Tsung Huang (ISCAS, 2016)

Fast realistic block-based refocusing for sparse light fields. - Li-Ren Huang; Yu-Wen Wang; Chao-Tsung Huang (ISCAS, 2016)

Fast Distribution Fitting for Parameter Estimation of Range-Weighted Neighborhood Filters. - Chao-Tsung Huang (IEEE Signal Process. Lett., 2016)

Robust Pseudo Random Fields for Light-Field Stereo Matching. - Chao-Tsung Huang (ICCV, 2017)

Fast Physically Correct Refocusing for Sparse Light Fields Using Block-Based Multi-Rate View Interpolation. - Chao-Tsung Huang; Yu-Wen Wang; Li-Ren Huang; Jui Chin; Liang-Gee Chen (IEEE Trans. Image Process., 2017)

A 95pJ/label Wide-Range Depth-Estimation Processor for Full-HD Light-Field Applications on FPGA. - Li-De Chen; Yu-Ta Lu; Yu-Ling Hsiao; Bo-Hsiang Yang; Wei-Chi Chen; Chao-Tsung Huang (A-SSCC, 2018)

A 320M Pixel/S Vlsi Architecture Design of Weighted Mode Filter for 4K Ultra-Hd Depth Upsampling. - Bo-Hsiang Yang; Li-De Chen; Chao-Tsung Huang (ICASSP, 2018)

System and VLSI Implementation of Phase-based View Synthesis. - Han-Chih Huang; Yu-Chih Wang; Wei-Chih Chen; Ping-Yen Lin; Chao-Tsung Huang (ICASSP, 2019)

eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference. - Chao-Tsung Huang; Yu-Chun Ding; Huan-Ching Wang; Chi-Wen Weng; Kai-Ping Lin; Li-Wei Wang 013; Li-De Chen (MICRO, 2019)

A 250mW 5.4G-Novel-Pixel/s Photorealistic Refocusing Processor for Full-HD Five-Camera Applications. - Po-Han Chen; Shu-Wen Yang; Shih-Yao Huang; Li-De Chen; Chao-Tsung Huang (VLSI Circuits, 2019)

Empirical Bayesian Light-Field Stereo Matching by Robust Pseudo Random Field Modeling. - Chao-Tsung Huang (IEEE Trans. Pattern Anal. Mach. Intell., 2019)

Ernet Family: Hardware-Oriented Cnn Models For Computational Imaging Using Block-Based Inference. - Chao-Tsung Huang (ICASSP, 2020)

FIR Filter Design and Implementation for Phase-Based Processing. - Shih-Yao Huang; Wei-Chih Chen; Chao-Tsung Huang (ICASSP, 2020)

Fast and Accurate Embedded DCNN for Rgb-D Based Sign Language Recognition. - Ching-Chen Wang; Ching-Te Chiu; Chao-Tsung Huang; Yu-Chun Ding; Li-Wei Wang 013 (ICASSP, 2020)

A Quality-Oriented Reconfigurable Convolution Engine Using Cross-Shaped Sparse Kernels for Highly-Parallel CNN Acceleration. - Chi-Wen Weng; Chao-Tsung Huang (AICAS, 2021)

RingCNN: Exploiting Algebraically-Sparse Ring Tensors for Energy-Efficient CNN-Based Computational Imaging. - Chao-Tsung Huang (ISCA, 2021)

Globally Assisted Instance Normalization for Bandwidth-Efficient Neural Style Transfer. - Hsiu-Pin Hsu; Chao-Tsung Huang (SiPS, 2021)

Real-Time Block-Based Embedded CNN for Gesture Classification on an FPGA. - Ching-Chen Wang; Yu-Chun Ding; Ching-Te Chiu; Chao-Tsung Huang; Yen-Yu Cheng; Shih-Yi Sun; Chih-Han Cheng; Hsueh-Kai Kuo (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Winograd-Based Highly-Parallel Convolution Engine for 8-bit CNN Acceleration. - Yong-Tai Chen; Yu-Feng Ou; Chao-Tsung Huang (AICAS, 2022)

A 4.6-8.3 TOPS/W 1.2-4.9 TOPS CNN-based Computational Imaging Processor with Overlapped Stripe Inference Achieving 4K Ultra-HD 30fps. - Yu-Chun Ding; Kai-Pin Lin; Chi-Wen Weng; Li-Wei Wang 013; Huan-Ching Wang; Chun-Yeh Lin; Yong-Tai Chen; Chao-Tsung Huang (ESSCIRC, 2022)

A HD 31fps 7×7-View Light-Field Factorization Processor for Dual-Layer 3D Factored Display. - Li-Qun Weng; Li-De Chen; Hao-Chien Cheng; An-You Zheng; Kai-Ping Lin; Chao-Tsung Huang (ISSCC, 2022)

Chaos LiDAR Based RGB-D Face Classification System With Embedded CNN Accelerator on FPGAs. - Ching-Te Chiu; Yu-Chun Ding; Wei-Chen Lin; Wei-Jyun Chen; Shu-Yun Wu; Chao-Tsung Huang; Chun-Yeh Lin; Chia-Yu Chang; Meng-Jui Lee; Shimazu Tatsunori; Tsung Chen; Fan-Yi Lin; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Biased Mixed-Precision Convolution Engine for Hardware-Efficient Computational Imaging CNN. - Hao-Jiun Tu; Yu-Feng Ou; Yong-Tai Chen; Chao-Tsung Huang (APSIPA ASC, 2023)

VISTA: A 704mW 4K-UHD CNN Processor for Video and Image Spatial/Temporal Interpolation Acceleration. - Kai-Ping Lin; Jia-Han Liu; Jyun-Yi Wu; Hong-Chuan Liao; Chao-Tsung Huang (ISSCC, 2023)

A 16nm 231mW Channel MLP Optimized Neural Processing Unit for 80.3% Top-1 ImageNet Classification Accuracy at 102fps. - Yong-Tai Chen; Hong-Chuan Liao; Hui-Yun Tsai; Kai-Feng Chang; Chao-Tsung Huang (A-SSCC, 2024)

VLSI Design of Light-Field Factorization for Dual-Layer Factored Display. - Li-De Chen; Li-Qun Weng; Hao-Chien Cheng; An-Yu Cheng; Kai-Ping Lin; Chao-Tsung Huang (IEEE Trans. Very Large Scale Integr. Syst., 2024)

2.5 A 16nm 5.7TOPS CNN Processor Supporting Bi-Directional FPN for Small-Object Detection on High-Resolution Videos. - Yu-Chun Ding; Chia-Yu Chang; Chun-Yeh Lin; Hui-Yun Tsai; Hao-Jiun Tu; Kai-Feng Chang; Yu-Ching Su; Tsung-Han Hsieh; Yu-Kuan Jian; Wen-Ching Chen; Nian-Shyang Chang; Chun-Pin Lin; et al. (ISSCC, 2025)

2.9 STEP: An 8K-60fps Space-Time Resolution-Enhancement Neural-Network Processor for Next-Generation Display and Streaming. - Kai-Ping Lin; Tong Wu; Chang-Pao Lin; Po-Wei Chen; Zhi-Jun Zhang; Win-San Khwa; Meng-Fan Chang; Chao-Tsung Huang (ISSCC, 2025)

High-Fidelity Depth Map Reconstruction System With RGB-Guided Super Resolution CNN and Cross-Calibrated Chaos LiDAR. - Yu-Chun Ding; Chia-Yu Chang; Pei-Rong Li; Chao-Tsung Huang; Yung-Chen Lin; Tsung Chen; Wei-Lun Lin; Cheng-Ting Lee; Fan-Yi Lin; Yuan-Hao Huang (IEEE Access, 2025)

Conscious Frontier Analysis Model: Learning-Based Path Planning for PointGoal Navigation. - Shri Harish Manoharan; Wei-Yu Chiu; Chao-Tsung Huang (IEEE Trans Autom. Sci. Eng., 2025)

Temporal Fusion: Continuous-Time Light Field Video Factorization. - Li-De Chen; Li-Qun Weng; Hao-Chien Cheng; An-Yu Cheng; Chao-Tsung Huang (IEEE Trans. Image Process., 2025)

Falcon: A Fused-Layer Accelerator With Layer-Wise Hybrid Inference Flow for Computational Imaging CNNs. - Yong-Tai Chen; Yen-Ting Chiu; Hao-Jiun Tu; Chao-Tsung Huang (IEEE Trans. Very Large Scale Integr. Syst., 2025)

VISTA: A Memory-Efficient CNN Processor for Video and Image Spatial/Temporal Interpolation Acceleration. - Kai-Ping Lin; Jia-Han Liu; Hong-Chuan Liao; Jyun-Yi Wu; Tong Wu; Chao-Tsung Huang (IEEE J. Solid State Circuits, 2025)