Area-efficient 3-input decimal adders using simplified carry and sum vectors. - Tso-Bing Juang; Hsin-Hao Peng; Chao-Tsung Kuo (VLSI-SoC, 2011)

A lower error antilogarithmic converter using novel four-region piecewise-linear approximation. - Chao-Tsung Kuo; Tso-Bing Juang (APCCAS, 2012)

Multifunction RNS Modulo 2n ± 1 Multipliers. - Tso-Bing Juang; Chao-Tsung Kuo; Go-Long Wu; Jian-Hao Huang (J. Circuits Syst. Comput., 2012)

Design and Circuit Implementation of Area-Delay-Product-Efficient Logarithmic Converters Using Mantissa-Bit Compensation Scheme. - Chao-Tsung Kuo (Circuits Syst. Signal Process., 2022)