Computing-in-Memory Architecture Based on Field-Free SOT-MRAM with Self-Reference Method. - Chao Wang 094; Zhaohao Wang; Yansong Xu; Jianlei Yang 001; Youguang Zhang; Weisheng Zhao (ISCAS, 2020)

Field-Free 3T2SOT MRAM for Non-Volatile Cache Memories. - Bi Wu; Chao Wang 094; Zhaohao Wang; Ying Wang 001; Deming Zhang; Dijun Liu; Youguang Zhang; Xiaobo Sharon Hu (IEEE Trans. Circuits Syst., 2020)

Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. - Bi Wu; Weisheng Zhao; Xiaobo Sharon Hu; Pengcheng Dai; Zhaohao Wang; Chao Wang 094; Ying Wang 001; Jianlei Yang 001; Yuanqing Cheng; Dijun Liu; Youguang Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Computing-in-Memory Paradigm Based on STT-MRAM with Synergetic Read/Write-Like Modes. - Chao Wang 094; Zhaohao Wang; Youguang Zhang; Weisheng Zhao (ISCAS, 2021)

Parallel Computing in Memory Paradigm based on Reconfigurable Spin-Orbit Torque. - Zhongkui Zhang; Chao Wang 094; Zhaohao Wang (NANOARCH, 2022)

Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM. - Zhengyi Hou; Zhaohao Wang; Chao Wang 094; Min Wang 033; You Wang 002; Xueyan Wang; Cenlin Duan; Jianlei Yang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Robust Time-based Error-Proofing Readout Scheme for MRAM. - Qianlei Ou; Shixing Li; Chao Wang 094; He Zhang 011; Zhaohao Wang (NANOARCH, 2023)

Layout Aware Optimization Methodology for SOT-MRAM Based on Technically Feasible Top-Pinned Magnetic Tunnel Junction Process. - Chao Wang 094; Zhaohao Wang; Zhongkui Zhang; Jiagao Feng; Youguang Zhang; Weisheng Zhao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Process and Design Considerations for Spin Orbit Torque MRAM. - Zhaohao Wang; Chao Wang 094; Min Wang 033; Chenyi Wang; Kaihua Cao; Chenlin Xu; Cong Zhang; Yunpeng Li; Hongxi Liu (APCCAS, 2024)

Area and Energy Efficient Short-Circuit-Logic-Based STT-MRAM Crossbar Array for Binary Neural Networks. - Chao Wang 094; Zhaohao Wang; Zhongkui Zhang; Youguang Zhang; Weisheng Zhao (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Variation Aware Evaluation Approach and Design Methodology for SOT-MRAM. - Chao Wang 094; Zhaohao Wang; Shixing Li; Zhongkui Zhang; Youguang Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

BSTCIM: A Balanced Symmetry Ternary Fully Digital In-MRAM Computing Macro for Energy Efficiency Neural Network. - Zhongzhen Tong; Chenghang Li; Chao Wang 094; Suteng Zhao; Qianyong Peng; Zhenyu Yan; Siqi Zhang; Daming Zhou; Zhaohao Wang; Xiaoyang Lin; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Approximate SOT-MRAM for Neural Network Acceleration with Superior Read Performance. - Yulong Qiu; Chao Wang 094; Zhongzhen Tong; Siyuan Cheng 021; Yueting Li; Zhaohao Wang (ISCAS, 2025)

Robust and Efficient NAND-Like TST-MRAM with Parallel Write/Read Operations and Reconfigurable PUF Mode. - Songhan Zhang; Xianzeng Guo; Yaling Wang; Chao Wang 094; Bi Wang 002; Zhaohao Wang (ISQED, 2025)

Thermal-Compensated MRAM Sensing: Dynamic TMR Stabilization Across Wide Temperature Range. - Tuo Zhang; Xinpeng Jiang; Chao Wang 094; Bi Wang 002; Hongxi Liu; Kaihua Cao; Xuan Li; Hui Jin; Geifei Wang; Zhaohao Wang; He Zhang 011; Weisheng Zhao (MOCAST, 2025)

A Novel Radiation-Hardened, Speed and Power Optimized Nonvolatile Latch for Aerospace Applications. - Shixing Li; Chenyi Wang; Zhongzhen Tong; Chao Wang 094; Bi Wang 002; Zhaohao Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Technically Feasible Robust Complementary SOT-MRAM Design for Improving the Area and Energy Efficiency. - Chao Wang 094; Zhongkui Zhang; Xiaoyang Xu; Xianzeng Guo; Qihang Gao; Zhaohao Wang; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)