Robust paradigm for diagnosing hold-time faults in scan chains. - Chao-Wen Tzeng; J.-J. Hsu; Shi-Yu Huang (IET Comput. Digit. Tech., 2007)

Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain. - Chao-Wen Tzeng; Shi-Yu Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Two-Gear Low-Power Scan Test. - Chao-Wen Tzeng; Shi-Yu Huang (ATS, 2008)

UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting. - Chao-Wen Tzeng; Shi-Yu Huang (IEEE Des. Test Comput., 2008)

A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques. - Chao-Wen Tzeng; Jheng-Syun Yang; Shi-Yu Huang (ACM Trans. Design Autom. Electr. Syst., 2008)

QC-Fill: An X-Fill method for quick-and-cool scan test. - Chao-Wen Tzeng; Shi-Yu Huang (DATE, 2009)

Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects. - Chao-Wen Tzeng; Han-Chia Cheng; Shi-Yu Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test. - Chao-Wen Tzeng; Shi-Yu Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. - Tsung-Yeh Li; Shi-Yu Huang; Hsuan-Jung Hsu; Chao-Wen Tzeng; Chih-Tsun Huang; Jing-Jia Liou; Hsi-Pin Ma; Po-Chiun Huang; Jenn-Chyou Bor; Cheng-Wen Wu; Ching-Cheng Tien; Mike Wang (DFT, 2010)

Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression. - Chao-Wen Tzeng; Shi-Yu Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A fully cell-based design for timing measurement of memory. - Yi-Chung Chang; Shi-Yu Huang; Chao-Wen Tzeng; Jack T. Yao (ITC, 2011)

Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property. - Ruo-Ting Ding; Shi-Yu Huang; Chao-Wen Tzeng; Shan-Chien Fang; Chia-Chien Weng (VLSI-DAT, 2012)

Case study of yield learning through in-house flow of volume diagnosis. - Pei-Ying Hsueh; Shuo-Fen Kuo; Chao-Wen Tzeng; Jih-Nung Lee; Chi-Feng Wu (VLSI-DAT, 2013)

Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism. - Ji-Wei Ker; Shi-Yu Huang; Chao-Wen Tzeng; Ding-Ming Kwai; Yung-Fa Chou (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping. - Pei-Ying Chao; Chao-Wen Tzeng; Shi-Yu Huang; Chia-Chieh Weng; Shan-Chien Fang (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Cell-Based Process Resilient Multiphase Clock Generation. - Ruo-Ting Ding; Shi-Yu Huang; Chao-Wen Tzeng (IEEE Trans. Very Large Scale Integr. Syst., 2013)

AC-Plus Scan Methodology for Small Delay Testing and Characterization. - Tsung-Yeh Li; Shi-Yu Huang; Hsuan-Jung Hsu; Chao-Wen Tzeng; Chih-Tsun Huang; Jing-Jia Liou; Hsi-Pin Ma; Po-Chiun Huang; Jenn-Chyou Bor; Ching-Cheng Tien; Chi-Hu Wang; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration. - Chao-Wen Tzeng; Shi-Yu Huang; Pei-Ying Chao (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Case study of process and design performance debugging with Digital Speed Sensor. - Chao-Wen Tzeng; Yin-Yen Chen; Jih-Nung Lee; Shu-Yi Kao (VLSI-DAT, 2015)