Delay budgeting in sequential circuit with application on FPGA placement. - Chao-Yang Yeh; Malgorzata Marek-Sadowska (DAC, 2003)

Minimum-Area Sequential Budgeting for FPGA. - Chao-Yang Yeh; Malgorzata Marek-Sadowska (ICCAD, 2003)

Sequential delay budgeting with interconnect prediction. - Chao-Yang Yeh; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Skew-programmable clock design for FPGA and skew-aware placement. - Chao-Yang Yeh; Malgorzata Marek-Sadowska (FPGA, 2005)

A sliding window scheme for accurate clock mesh analysis. - Hongyu Chen; Chao-Yang Yeh; Gustavo R. Wilke; Subodh M. Reddy; Hoa-van Nguyen; William W. Walker; Rajeev Murgai (ICCAD, 2005)

Timing-aware power noise reduction in layout. - Chao-Yang Yeh; Malgorzata Marek-Sadowska (ICCAD, 2005)

Clock Distribution Architectures: A Comparative Study. - Chao-Yang Yeh; Gustavo R. Wilke; Hongyu Chen; Subodh M. Reddy; Hoa-van Nguyen; Takashi Miyoshi; William W. Walker; Rajeev Murgai (ISQED, 2006)

Timing-Aware Power-Noise Reduction in Placement. - Chao-Yang Yeh; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC. - Ashish Nayak; HsinChen Chen; Hugh Mair; Rolf Lagerquist; Tao Chen; Anand Rajagopalan; Gordon Gammie; Ramu Madhavaram; Madhur Jagota; C. J. Chung; Jenny Wiedemeier; Bala Meera; et al. (ISSCC, 2022)