An Approach to Agent Path Planning Under Temporal Logic Constraints. - Chaofeng Yu; Nan Zhang 001; Zhenhua Duan; Cong Tian (COCOON (2), 2023)

Verifying Chips Design at RTL Level. - Wu Wang; Nan Zhang 001; Cong Tian; Zhenhua Duan; Zhijie Xu; Chaofeng Yu (TASE, 2023)

Wavelet-Based Time-Reassigned Synchroextracting Transform With Application to Fault Diagnosis of Flexible Thin-Wall Bearing. - Yanjiang Yu; Xuezhi Zhao; Chaofeng Yu (IEEE Trans. Instrum. Meas., 2023)

A proof system for unified temporal logic. - Nan Zhang 001; Chaofeng Yu; Zhenhua Duan; Cong Tian (Theor. Comput. Sci., 2023)

Verifying chip designs at RTL level. - Nan Zhang 001; Zhijie Xu; Zhenhua Duan; Cong Tian; Wu Wang; Chaofeng Yu (Sci. Comput. Program., 2025)

SAT-based bounded model checking for propositional projection temporal logic. - Zhenhua Duan; Cong Tian; Nan Zhang 001; Chaofeng Yu; Mengfei Yang; Jia He (Theor. Comput. Sci., 2025)