A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture. - Zi Wang; Jinshan Yue; Chaojie He; Zhuoyu Dai; Feibin Xiang; Zhaori Cong; Yifan He 003; Xiaoyu Feng; Yongpan Liu (ISCAS, 2023)

A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture. - Jinshan Yue; Chaojie He; Zi Wang; Zhaori Cong; Yifan He 002; Mufeng Zhou; Wenyu Sun; Xueqing Li 002; Chunmeng Dou; Feng Zhang 014; Huazhong Yang; Yongpan Liu; et al. (ISSCC, 2023)

A Scalable Small-Footprint Time-Space-Pipelined Architecture for Reservoir Computing. - Zhuoyu Dai; Feibin Xiang; Chaojie He; Zi Wang; Woyu Zhang; Yi Li 049; Jinshan Yue; Dashan Shang (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design. - Chaojie He; Zi Wang; Feibin Xiang; Zhuoyu Dai; Yifan He 003; Jinshan Yue; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture. - Shengzhe Yan; Jinshan Yue; Chaojie He; Zi Wang; Zhaori Cong; Yifan He 002; Mufeng Zhou; Wenyu Sun; Xueqing Li 002; Chunmeng Dou; Feng Zhang 014; Huazhong Yang; et al. (IEEE J. Solid State Circuits, 2024)