FPGA Accelerator for Radar-Based Human Activity Recognition. - Kangjie Long; Chaolin Rao; Xiangyu Zhang 002; Wen Bin Ye 001; Xin Lou (AICAS, 2022)

An Energy Efficient Precision Scalable Computation Array for Neural Radiance Field Accelerator. - Chaolin Rao; Haochuan Wan; Yueyang Zheng; Pingqiang Zhou; Xin Lou (APCCAS, 2022)

SME: A Systolic Multiply-accumulate Engine for MLP-based Neural Network. - Haochuan Wan; Chaolin Rao; Yueyang Zheng; Pingqiang Zhou; Xin Lou (APCCAS, 2022)

A Multi-precision Multiply-Accumulation Array. - Chaolin Rao; Yueyang Zheng; Haochuan Wan (ISOCC, 2022)

An RRAM-based Neural Radiance Field Processor. - Yueyang Zheng; Chaolin Rao; Haochuan Wan; Yuliang Zhou; Pingqiang Zhou; Jingyi Yu; Xin Lou (SOCC, 2022)

ICARUS: A Lightweight Neural Plenoptic Rendering Architecture. - Chaolin Rao; Huangjie Yu; Haochuan Wan; Jindong Zhou; Yueyang Zheng; Yu Ma; Anpei Chen; Minye Wu; Binzhe Yuan; Pingqiang Zhou; Xin Lou; Jingyi Yu (CoRR, 2022)

ICARUS: A Specialized Architecture for Neural Radiance Fields Rendering. - Chaolin Rao; Huangjie Yu; Haochuan Wan; Jindong Zhou; Yueyang Zheng; Minye Wu; Yu Ma; Anpei Chen; Binzhe Yuan; Pingqiang Zhou; Xin Lou; Jingyi Yu (ACM Trans. Graph., 2022)

A Systolic Array with Activation Stationary Dataflow for Deep Fully-Connected Networks. - Haochuan Wan; Chaolin Rao; Yueyang Zheng; Pingqiang Zhou; Xin Lou (AICAS, 2023)

An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation. - Chaolin Rao; Qing Wu 001; Pingqiang Zhou; Jingyi Yu; Yuyao Zhang; Xin Lou (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Low-Power Reconfigurable FIR Filter Design Based on Common Operation Sharing. - Ling Zhang 010; Chaolin Rao; Xin Lou (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Analysis and Design of Precision-Scalable Computation Array for Efficient Neural Radiance Field Rendering. - Kangjie Long; Chaolin Rao; Yunxiang He; Zhechen Yuan; Pingqiang Zhou; Jingyi Yu; Xin Lou (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 0.59μJ/pixel High-throughput Energy-efficient Neural Volume Rendering Accelerator on FPGA. - Zhechen Yuan; Binzhe Yuan; Yuhan Gu; Yueyang Zheng; Yunxiang He; Xuexin Wang; Chaolin Rao; Pingqiang Zhou; Jingyi Yu; Xin Lou (CICC, 2024)

FPGA Accelerator for Human Activity Recognition Based on Radar. - Kangjie Long; Chaolin Rao; Xiangyu Zhang 002; Wenbin Ye 001; Xin Lou (IEEE Trans. Circuits Syst. II Express Briefs, 2024)