4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. - Penny Li; Jinuk Luke Shin; Georgios K. Konstadinidis; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; et al. (ISSCC, 2015)

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. - Georgios K. Konstadinidis; Hongping Penny Li; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; Vijay Srinivasan; et al. (IEEE J. Solid State Circuits, 2016)

Multi-Scale Feedback Feature Refinement U-Net for Medical Image Segmentation. - Xiaofei Qin; Minmin Xu; Chaoyang Zheng; Changxiang He; Xuedian Zhang (ICME, 2021)

A 400M-510MHz On-Chip Transformer-Based RF Power Amplifier with 22.5dBm Output Power and 48% PAE. - Chaoyang Zheng; Zhipeng Chen; Jianhua Lu; Yan Ma; Yumei Huang; Zhiliang Hong (ASICON, 2023)

Global exponential synchronization of complex networks with reaction diffusions and finite distributed delays coupling. - Yun Xing; Chaoyang Zheng; Yin Sheng; Zhigang Zeng (Neurocomputing, 2024)

A Low-Power, Compact, 0.1-5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR. - Cong Tao; Liangbo Lei; Chaoyang Zheng; Yumei Huang; Zhiliang Hong; Xiaoyang Zeng (IEEE J. Solid State Circuits, 2024)