Digital IC Design of a 45nm CMOS Chua Encryption Architecture for Resource Limited Devices. - Charanya K. Rao; Ravi Monani; Ava Hedayatipour (ISVLSI, 2025)

ASIC Design Flow Using Simulink and Cadence Digital IC Design Tools. - Charanya K. Rao; Ashmitha Talluri; Ava Hedayatipour (ISVLSI, 2025)