Integrated-Circuit Logarithmic Arithmetic Units. - Jeffrey H. Lang; Charles A. Zukowski; Richard O. LaMaire; Chae H. An (IEEE Trans. Computers, 1985)

Relaxing Bounds for Linear RC Mesh Circuits. - Charles A. Zukowski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

Variable reduction in MOS timing models. - Charles A. Zukowski; De-Ping Chen (ICCD, 1988)

A matched-delay CMOS TDM multiplexer cell. - Charles A. Zukowski; Kevin Shum (ICCD, 1988)

Continuous Models for Communication Density Constraints on Multiprocessor Performance. - Lance A. Glasser; Charles A. Zukowski (IEEE Trans. Computers, 1988)

Measuring Error Propagation in Waveform Relaxation Algorithms. - Charles A. Zukowski; George Gristede; Albert E. Ruehli (ICCAD, 1990)

VLSI Implementation of Routing Tables: Tries and CAMs. - Tong-Bi Pei; Charles A. Zukowski (INFOCOM, 1991)

Implementing a High-Frequency Pattern Generator Based on Combinational Merging. - Charles A. Zukowski; Ying-Wen Bai (ICCD, 1992)

Putting routing tables in silicon. - Tong-Bi Pei; Charles A. Zukowski (IEEE Netw., 1992)

High-speed parallel CRC circuits in VLSI. - Tong-Bi Pei; Charles A. Zukowski (IEEE Trans. Commun., 1992)

Analysis and Control of Timing Jitter in Digital Logic Arising from Noise Voltage Sources. - Perng-Shyong Lin; Charles A. Zukowski (ICCD, 1993)

Jitter Due to Signal History in Digital Logic Circuits and Its Control Strategies. - Perng-Shyong Lin; Charles A. Zukowski (ISCAS, 1993)

Delay-time bounds and waveform bounds for RLCG ladder networks. - Ying-Wen Bai; Charles A. Zukowski (Annual Simulation Symposium, 1994)

Generic Queue Scheduling: Concepts and VLSI. - Paul Landsberg; Charles A. Zukowski (INFOCOM, 1994)

Buffer size trade-offs in input/output buffered ATM switches under various conditions. - Hong Shi; Naeem Abbasi; Charles A. Zukowski; Omar Wing (ICCCN, 1995)

CMOS Transistor Sizing for Minimization of Energy-Delay Product. - Christophe Tretz; Charles A. Zukowski (Great Lakes Symposium on VLSI, 1996)

VLSI Design Optimization of Input/Output-Buffered Broadband ATM Switches. - Hong Shi; Charles A. Zukowski; Omar Wing (INFOCOM, 1996)

Accuracy management for mixed-mode digital VLSI simulation. - Gary L. Dare; Charles A. Zukowski (ACM Great Lakes Symposium on VLSI, 2000)

Application of dynamic power supply scaling in a low-energy ATM interface. - S. Henry Li; Charles A. Zukowski (ISCAS, 2000)

An assessment of on-line engineering design problem presentation strategies. - Anthony A. Renshaw; Joshua H. Reibel; Charles A. Zukowski; Katie Penn; Robert O. McClintock; Morton B. Friedman (IEEE Trans. Educ., 2000)

A custom FPGA for the simulation of gene regulatory networks. - Ilias Tagkopoulos; Charles A. Zukowski; German Cavelier; Dimitris Anastassiou (ACM Great Lakes Symposium on VLSI, 2003)

Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage. - Ali Bastani; Charles A. Zukowski (ACM Great Lakes Symposium on VLSI, 2004)

Characterization of logic circuit techniques for high leakage CMOS technologies. - Phillip Chin; Charles A. Zukowski; George Gristede; Stephen V. Kosonocky (ACM Great Lakes Symposium on VLSI, 2004)

Characterization of monotonic static CMOS gates in a 65nm technology. - Ali Bastani; Charles A. Zukowski (ACM Great Lakes Symposium on VLSI, 2005)

Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies. - Phillip Chin; Charles A. Zukowski; George Gristede; Stephen V. Kosonocky (Integr., 2005)

Monotonic static CMOS tradeoffs in sub-100nm technologies. - Ali Bastani; Charles A. Zukowski (ACM Great Lakes Symposium on VLSI, 2006)

A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology. - Ali Bastani; Charles A. Zukowski (ISQED, 2006)

Characteristics of MS-CMOS logic in sub-32nm technologies. - Kagan Irez; Jiaping Hu; Charles A. Zukowski (ACM Great Lakes Symposium on VLSI, 2010)