Testing generality in JANUS: a multi-lingual speech translation system. - Louise Osterholtz; Charles Augustine; Arthur E. McNair; Ivica Rogina; Hiroaki Saito 001; Tilo Sloboda; Joe Tebelskis; Alex Waibel (ICASSP, 1992)

Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. - Jing Li 073; Charles Augustine; Sayeef S. Salahuddin; Kaushik Roy 001 (DAC, 2008)

Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems. - Nilanjan Banerjee; Charles Augustine; Kaushik Roy 001 (DFT, 2008)

A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems. - Charles Augustine; Behtash Behin-Aein; Xuanyao Fong; Kaushik Roy 001 (ASP-DAC, 2009)

PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices. - Charles Augustine; Arijit Raychowdhury; Yunfei Gao; Mark S. Lundstrom; Kaushik Roy 001 (ISQED, 2009)

Data-dependant sense-amplifier flip-flop for low power applications. - Farshad Moradi; Charles Augustine; Ashish Goel; Georgios Karakonstantis; Tuan Vu Cao; Dag T. Wisland; Hamid Mahmoodi; Kaushik Roy 001 (CICC, 2010)

A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique. - Georgios Karakonstantis; Charles Augustine; Kaushik Roy 001 (IOLTS, 2010)

Low-power functionality enhanced computation architecture using spin-based devices. - Charles Augustine; Georgios Panagopoulos; Behtash Behin-Aein; Srikant Srinivasan; Angik Sarkar; Kaushik Roy 001 (NANOARCH, 2011)

Energy efficient many-core processor for recognition and mining using spin-based memory. - Rangharajan Venkatesan; Vinay K. Chippa; Charles Augustine; Kaushik Roy 001; Anand Raghunathan (NANOARCH, 2011)

Cognitive computing with spin-based neural networks. - Mrigank Sharad; Charles Augustine; Georgios Panagopoulos; Kaushik Roy 001 (DAC, 2012)

A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach. - Georgios Panagopoulos; Charles Augustine; Kaushik Roy 001 (DATE, 2012)

Spin based neuron-synapse module for ultra low power programmable computational networks. - Mrigank Sharad; Charles Augustine; Georgios Panagopoulos; Kaushik Roy 001 (IJCNN, 2012)

TapeCache: a high density, energy efficient cache based on domain wall memory. - Rangharajan Venkatesan; Vivek Joy Kozhikkottu; Charles Augustine; Arijit Raychowdhury; Kaushik Roy 001; Anand Raghunathan (ISLPED, 2012)

Ultra low energy analog image processing using spin based neurons. - Mrigank Sharad; Charles Augustine; Georgios Panagopoulos; Kaushik Roy 001 (NANOARCH, 2012)

Proposal For Neuromorphic Hardware Using Spin Devices - Mrigank Sharad; Charles Augustine; Georgios Panagopoulos; Kaushik Roy 001 (CoRR, 2012)

Minimum supply voltage for sequential logic circuits in a 22nm technology. - Chia-Hsiang Chen; Keith A. Bowman; Charles Augustine; Zhengya Zhang; Jim Tschanz (ISLPED, 2013)

Dual pillar spin-transfer torque MRAMs for low power applications. - Niladri Narayan Mojumder; Xuanyao Fong; Charles Augustine; Sumeet Kumar Gupta; Sri Harsha Choday; Kaushik Roy 001 (ACM J. Emerg. Technol. Comput. Syst., 2013)

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. - Carlos Tokunaga; Joseph F. Ryan 002; Charles Augustine; Jaydeep P. Kulkarni; Yi-Chun Shih; Stephen T. Kim; Rinkle Jain; Keith A. Bowman; Arijit Raychowdhury; Muhammad M. Khellah; James W. Tschanz; Vivek De (ISSCC, 2014)

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. - Stephen T. Kim; Yi-Chun Shih; Kaushik Mazumdar; Rinkle Jain; Joseph F. Ryan 002; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (ISSCC, 2015)

4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. - Jaydeep P. Kulkarni; Carlos Tokunaga; Paolo A. Aseron; Trang Nguyen; Charles Augustine; James W. Tschanz; Vivek De (ISSCC, 2015)

Forward table-based presynaptic event-triggered spike-timing-dependent plasticity. - Bruno U. Pedroni; Sadique Sheik; Siddharth Joshi 001; Georgios Detorakis; Somnath Paul; Charles Augustine; Emre Neftci; Gert Cauwenberghs (BioCAS, 2016)

Membrane-dependent neuromorphic learning rule for unsupervised spike pattern detection. - Sadique Sheik; Somnath Paul; Charles Augustine; Gert Cauwenberghs (BioCAS, 2016)

Synaptic sampling in hardware spiking neural networks. - Sadique Sheik; Somnath Paul; Charles Augustine; Chinnikrishna Kothapalli; Muhammad M. Khellah; Gert Cauwenberghs; Emre Neftci (ISCAS, 2016)

8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. - Minki Cho; Stephen T. Kim; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (ISSCC, 2016)

Event-driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines. - Emre Neftci; Charles Augustine; Somnath Paul; Georgios Detorakis (CoRR, 2016)

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. - Stephen T. Kim; Yi-Chun Shih; Kaushik Mazumdar; Rinkle Jain; Joseph F. Ryan 002; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (IEEE J. Solid State Circuits, 2016)

A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. - Jaydeep P. Kulkarni; Carlos Tokunaga; Paolo A. Aseron; Trang Nguyen; Charles Augustine; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2016)

Cache Design with Domain Wall Memory. - Rangharajan Venkatesan; Vivek Joy Kozhikkottu; Mrigank Sharad; Charles Augustine; Arijit Raychowdhury; Kaushik Roy 001; Anand Raghunathan (IEEE Trans. Computers, 2016)

Event-driven random backpropagation: Enabling neuromorphic deep learning machines. - Emre Neftci; Charles Augustine; Somnath Paul; Georgios Detorakis (ISCAS, 2017)

Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning. - Georgios Detorakis; Sadique Sheik; Charles Augustine; Somnath Paul; Bruno U. Pedroni; Nikil D. Dutt; Jeffrey L. Krichmar; Gert Cauwenberghs; Emre Neftci (CoRR, 2017)

Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. - Minki Cho; Stephen T. Kim; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (IEEE J. Solid State Circuits, 2017)

Small-footprint Spiking Neural Networks for Power-efficient Keyword Spotting. - Bruno U. Pedroni; Sadique Sheik; Hesham Mostafa; Somnath Paul; Charles Augustine; Gert Cauwenberghs (BioCAS, 2018)

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks. - Xiaowei Wang; Jiecao Yu; Charles Augustine; Ravi R. Iyer 001; Reetuparna Das (HPCA, 2019)

A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response. - Zakir K. Ahmed 001; Harish K. Krishnamurthy; Charles Augustine; Xiaosen Liu; Sheldon Weng; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2019)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)

25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS. - Suyoung Bang; Wootaek Lim; Charles Augustine; Andres Malavasi; Muhammad M. Khellah; James W. Tschanz; Vivek De (ISSCC, 2020)

2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. - Charles Augustine; Somnath Paul; Turbo Majumder; James W. Tschanz; Muhammad M. Khellah; Vivek De (VLSI Circuits, 2020)

Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. - Jaydeep P. Kulkarni; Andres Malavasi; Charles Augustine; Carlos Tokunaga; Jim Tschanz; Muhammad M. Khellah; Vivek De (VLSI Circuits, 2020)

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. - Somnath Paul; Turbo Majumder; Charles Augustine; Andres F. Malavasi; S. Usirikayala; Raghavan Kumar; Jisna Kollikunnel; S. Chhabra; Satish Yada; M. L. Barajas; Carlos Ornelas; Dan Lake; et al. (VLSI Circuits, 2020)

A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response. - Khondker Zakir Ahmed 001; Harish K. Krishnamurthy; Charles Augustine; Xiaosen Liu; Sheldon Weng; Krishnan Ravichandran; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2020)

Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. - Xiaowei Wang; Vidushi Goyal; Jiecao Yu; Valeria Bertacco; Andrew Boutros; Eriko Nurvitadhi; Charles Augustine; Ravi R. Iyer 001; Reetuparna Das (FCCM, 2021)

Cache Compression with Efficient in-SRAM Data Comparison. - Xiaowei Wang; Charles Augustine; Eriko Nurvitadhi; Ravi R. Iyer 001; Li Zhao 002; Reetuparna Das (NAS, 2021)

All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP. - Charles Augustine; A. Afzal; U. Misgar; Abdullah A. Owahid; A. Raman; K. Subramanian; Feroze Merchant; James W. Tschanz; Muhammad M. Khellah (VLSI Circuits, 2021)

A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS. - Charles Augustine; Pascal Meinerzhagen; Wootaek Lim; A. Veerabathini; M. Bright; K. Mojjada; Jim Tschanz; Muhammad M. Khellah; Vivek De (VLSI Technology and Circuits, 2023)

ISLPED 2022: An Experience of a Hybrid Conference in the Time of COVID-19. - Charles Augustine; Hai Helen Li (IEEE Des. Test, 2023)

Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks. - Charles Eckert; Arun Subramaniyan 001; Xiaowei Wang; Charles Augustine; Ravishankar Iyer 001; Reetuparna Das (IEEE Trans. Computers, 2023)

8.8 Fine-Grained Spatial and Temporal Thermal Profiling of a 16nm CMOS Buck Converter and SoC Load-Current Emulator Using Low-Voltage Micron-Scale Thermal Sensors. - Zakir K. Ahmed 001; Suhwan Kim 002; Charles Augustine; Harish K. Krishnamurthy; Krishnan Ravichandran; James W. Tschanz; Vivek De (ISSCC, 2025)

NEXUS: A 28nm 3.3pJ/SOP 16-Core Spiking Neural Network With a Diamond Topology for Real-Time Data Processing. - Maryam Sadeghi; Yasser Rezaeiyan; Darío Fernández Khatiboun; Sherif Eissa; Federico Corradi; Charles Augustine; Farshad Moradi (IEEE Trans. Biomed. Circuits Syst., 2025)