A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop. - Socrates D. Vamvakos; Charles Boecker; Eric Groen; Alvin Wang; Shaishav Desai; Scott Irwin; Vithal Rao; Aldo Bottelli; Jawji Chen; Xiaole Chen; Prashant Choudhary; Kuo-Chiang Hsieh; et al. (CICC, 2014)

A 4×112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET. - Haidang Lin; Charles Boecker; Masum Hossain; Shankar Tangirala; Roxanne Vu; Socrates D. Vamvakos; Eric Groen; Simon Li; Prashant Choudhary; Nanyan Wang; Masumi Shibata; Hossein Taghavi; et al. (VLSI Circuits, 2020)