DRNG: DRAM-based random number generation using its startup value behavior. - Charles Eckert; Fatemeh Tehranipoor; John A. Chandy (MWSCAS, 2017)

A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration. - Jingcheng Wang; Xiaowei Wang; Charles Eckert; Arun Subramaniyan 001; Reetuparna Das; David T. Blaauw; Dennis Sylvester (ISSCC, 2019)

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks. - Charles Eckert; Xiaowei Wang; Jingcheng Wang; Arun Subramaniyan 001; Dennis Sylvester; David T. Blaauw; Reetuparna Das; Ravi R. Iyer 001 (IEEE Micro, 2019)

A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing. - Jingcheng Wang; Xiaowei Wang; Charles Eckert; Arun Subramaniyan 001; Reetuparna Das; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2020)

In-SRAM Computing for Neural Network Acceleration - Charles Eckert (2022)

Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks. - Charles Eckert; Arun Subramaniyan 001; Xiaowei Wang; Charles Augustine; Ravishankar Iyer 001; Reetuparna Das (IEEE Trans. Computers, 2023)