LSI Yield Modeling and Process Monitoring. - Charles H. Stapper (IBM J. Res. Dev., 1976)

Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product. - Charles H. Stapper; A. N. McLaren; M. Dreckmann (IBM J. Res. Dev., 1980)

Modeling of Integrated Circuit Defect Sensitivities. - Charles H. Stapper (IBM J. Res. Dev., 1983)

Modeling of Defects in Integrated Circuit Photolithographic Patterns. - Charles H. Stapper (IBM J. Res. Dev., 1984)

Yield Model for Fault Clusters Within Integrated Circuits. - Charles H. Stapper (IBM J. Res. Dev., 1984)

Yield of VLSI circuits: myths vs. reality (panel). - Andrzej J. Strojwas; Clark Beck; Dennis Buss; Tülin Erdim Mangir; Charles H. Stapper (DAC, 1986)

Large-Area Fault Clusters and Fault Tolerance in VLSI Circuits: A Review. - Charles H. Stapper (IBM J. Res. Dev., 1989)

Simulation of spatial fault distributions for integrated circuit yield estimations. - Charles H. Stapper (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC. - Howard L. Kalter; Charles H. Stapper; John E. Barth Jr.; John DiLorenzo; Charles E. Drake; John A. Fifield; Gordon A. Kelley; Scott C. Lewis; Willem B. van der Hoeven; James A. Yankosky (IEEE J. Solid State Circuits, 1990)

Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement. - Charles H. Stapper (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

High-speed on-chip ECC for synergistic fault-tolerance memory chips. - John A. Fifield; Charles H. Stapper (IEEE J. Solid State Circuits, 1991)

A New Statistical Approach for Fault-Tolerant VLSI Systems. - Charles H. Stapper (FTCS, 1992)

Synergistic Fault-Tolerance for Memory Chips. - Charles H. Stapper; Hsing-San Lee (IEEE Trans. Computers, 1992)

Yield Model for ASIC and Processor Chips. - Charles H. Stapper; J. A. Patrick; R. J. Rosner (DFT, 1993)

A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits. - Israel Koren; Zahava Koren; Charles H. Stapper (IEEE Trans. Computers, 1993)

Improved Yield Models for Fault-Tolerant Memory Chips. - Charles H. Stapper (IEEE Trans. Computers, 1993)

On Fractal Yield Models: A Statistical Paradox. - Charles H. Stapper; A. J. Rideout (DFT, 1994)

A statistical study of defect maps of large area VLSI IC's. - Israel Koren; Zahava Koren; Charles H. Stapper (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Multipurpose DRAM architecture for optimal power, performance, and product flexibility. - Wayne F. Ellis; John E. Barth Jr.; Sri Divakaruni; Jeffrey H. Dreibelbis; Anatol Furman; Erik L. Hedberg; Hsing-San Lee; Thomas M. Maffitt; Christopher P. Miller; Charles H. Stapper; Howard L. Kalter (IBM J. Res. Dev., 1995)