Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. - Charles J. Alpert; Andrew B. Kahng (DAC, 1993)

Minimum Density Interconneciton Trees. - Charles J. Alpert; Jason Cong; Andrew B. Kahng; Gabriel Robins; Majid Sarrafzadeh (ISCAS, 1993)

A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing. - Charles J. Alpert; T. C. Hu; Jen-Hsin Huang; Andrew B. Kahng (ISCAS, 1993)

Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming. - Charles J. Alpert; Andrew B. Kahng (DAC, 1994)

A general framework for vertex orderings, with applications to netlist clustering. - Charles J. Alpert; Andrew B. Kahng (ICCAD, 1994)

On the Minimum Density Interconnection Tree Problem. - Charles J. Alpert; Jason Cong; Andrew B. Kahng; Gabriel Robins; Majid Sarrafzadeh (VLSI Design, 1994)

Spectral Partitioning: The More Eigenvectors, The Better. - Charles J. Alpert; So-Zen Yao (DAC, 1995)

Recent directions in netlist partitioning: a survey. - Charles J. Alpert; Andrew B. Kahng (Integr., 1995)

Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. - Charles J. Alpert; T. C. Hu; Dennis J.-H. Huang; Andrew B. Kahng; David R. Karger (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Multiway partitioning via geometric embeddings, orderings, and dynamic programming. - Charles J. Alpert; Andrew B. Kahng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

A general framework for vertex orderings with applications to circuit clustering. - Charles J. Alpert; Andrew B. Kahng (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Quadratic Placement Revisited. - Charles J. Alpert; Tony F. Chan; Dennis J.-H. Huang; Igor L. Markov; Kenneth Yan (DAC, 1997)

Wire Segmenting for Improved Buffer Insertion. - Charles J. Alpert; Anirudh Devgan (DAC, 1997)

Faster minimization of linear wirelength for global placement. - Charles J. Alpert; Tony F. Chan; Dennis J.-H. Huang; Andrew B. Kahng; Igor L. Markov; Pep Mulet; Kenneth Yan (ISPD, 1997)

The ISPD98 circuit benchmark suite. - Charles J. Alpert (ISPD, 1998)

Faster minimization of linear wirelength for global placement. - Charles J. Alpert; Tony F. Chan; Andrew B. Kahng; Igor L. Markov; Pep Mulet (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Multilevel circuit partitioning. - Charles J. Alpert; Jen-Hsin Huang; Andrew B. Kahng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Buffer Insertion with Accurate Gate and Interconnect Delay Computation. - Charles J. Alpert; Anirudh Devgan; Stephen T. Quay (DAC, 1999)

Is wire tapering worthwhile? - Charles J. Alpert; Anirudh Devgan; Stephen T. Quay (ICCAD, 1999)

Partitioning with terminals: a "new" problem and new benchmarks. - Charles J. Alpert; Andrew E. Caldwell; Andrew B. Kahng; Igor L. Markov (ISPD, 1999)

Spectral Partitioning with Multiple Eigenvectors. - Charles J. Alpert; Andrew B. Kahng; So-Zen Yao (Discret. Appl. Math., 1999)

Buffer insertion for noise and delay optimization. - Charles J. Alpert; Anirudh Devgan; Stephen T. Quay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Analytical Engines are Unnecessary in Top-down Partitioning-based Placement. - Charles J. Alpert; Andrew E. Caldwell; Tony F. Chan; Dennis J.-H. Huang; Andrew B. Kahng; Igor L. Markov; M. S. Moroz (VLSI Design, 1999)

An "Effective" Capacitance Based Delay Metric for RC Interconnect. - Chandramouli V. Kashyap; Charles J. Alpert; Anirudh Devgan (ICCAD, 2000)

A two moment RC delay metric for performance optimization. - Charles J. Alpert; Anirudh Devgan; Chandramouli V. Kashyap (ISPD, 2000)

Datapath routing based on a decongestion metric. - Suresh Raman; Sachin S. Sapatnekar; Charles J. Alpert (ISPD, 2000)

Hypergraph partitioning with fixed vertices [VLSI CAD]. - Charles J. Alpert; Andrew E. Caldwell; Andrew B. Kahng; Igor L. Markov (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. - Charles J. Alpert; Andrew B. Kahng; Bao Liu 001; Ion I. Mandoiu; Alexander Zelikovsky (ICCAD, 2001)

Buffered Steiner trees for difficult instances. - Charles J. Alpert; Milos Hrkic; Jiang Hu; Andrew B. Kahng; John Lillis; Bao Liu 001; Stephen T. Quay; Sachin S. Sapatnekar; A. J. Sullivan; Paul Villarrubia (ISPD, 2001)

A clock distribution network for microprocessors. - Phillip J. Restle; Timothy G. McNamara; David A. Webber; Peter J. Camporese; Kwok F. Eng; Keith A. Jenkins; David H. Allen; Michael J. Rohn; Michael P. Quaranta; David W. Boerstler; Charles J. Alpert; Craig A. Carter; et al. (IEEE J. Solid State Circuits, 2001)

Interconnect synthesis without wire tapering. - Charles J. Alpert; Anirudh Devgan; John P. Fishburn; Stephen T. Quay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

RC delay metrics for performance optimization. - Charles J. Alpert; Anirudh Devgan; Chandramouli V. Kashyap (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Steiner tree optimization for buffers, blockages, and bays. - Charles J. Alpert; Gopal Gandham; Jiang Hu; José Luis Neves; Stephen T. Quay; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Free space management for cut-based placement. - Charles J. Alpert; Gi-Joon Nam; Paul Villarrubia (ICCAD, 2002)

Optimal buffered routing path constructions for single and multiple clock domain systems. - Soha Hassoun; Charles J. Alpert; Meera Thiagarajan (ICCAD, 2002)

PERI: a technique for extending delay and slew metrics to ramp inputs. - Chandramouli V. Kashyap; Charles J. Alpert; Frank Liu 001; Anirudh Devgan (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

Probability-driven routing in a datapath environment. - Suresh Raman; Sachin S. Sapatnekar; Charles J. Alpert (Integr., 2002)

Correction to "interconnect synthesis without wire tapering". - Charles J. Alpert; Anirudh Devgan; John P. Fishburn; Stephen T. Quay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Delay and slew metrics using the lognormal distribution. - Charles J. Alpert; Frank Liu 001; Chandramouli V. Kashyap; Anirudh Devgan (DAC, 2003)

Porosity aware buffered steiner tree construction. - Charles J. Alpert; Gopal Gandham; Milos Hrkic; Jiang Hu; Stephen T. Quay (ISPD, 2003)

Closed form expressions for extending step delay and slew metrics to ramp inputs. - Chandramouli V. Kashyap; Charles J. Alpert; Frank Liu 001; Anirudh Devgan (ISPD, 2003)

A practical methodology for early buffer and wire resource allocation. - Charles J. Alpert; Jiang Hu; Sachin S. Sapatnekar; Paul Villarrubia (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Minimum buffered routing with bounded capacitive load for slew rate and reliability control. - Charles J. Alpert; Andrew B. Kahng; Bao Liu 001; Ion I. Mandoiu; Alexander Zelikovsky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Effective free space management for cut-based placement via analytical constraint generation. - Charles J. Alpert; Gi-Joon Nam; Paul G. Villarrubia (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Guest editorial. - Charles J. Alpert; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Optimal path routing in single- and multiple-clock domain systems. - Soha Hassoun; Charles J. Alpert (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Buffer insertion with adaptive blockage avoidance. - Jiang Hu; Charles J. Alpert; Stephen T. Quay; Gopal Gandham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. - Weiping Shi; Zhuo Li 001; Charles J. Alpert (ASP-DAC, 2004)

A place and route aware buffered Steiner tree construction. - Cliff C. N. Sze; Jiang Hu; Charles J. Alpert (ASP-DAC, 2004)

Fast and flexible buffer trees that navigate the physical layout environment. - Charles J. Alpert; Milos Hrkic; Jiang Hu; Stephen T. Quay (DAC, 2004)

A fast algorithm for identifying good buffer insertion candidate locations. - Charles J. Alpert; Milos Hrkic; Stephen T. Quay (ISPD, 2004)

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. - Charles J. Alpert; Chris C. N. Chu; Gopal Gandham; Milos Hrkic; Jiang Hu; Chandramouli V. Kashyap; Stephen T. Quay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Porosity-aware buffered Steiner tree construction. - Charles J. Alpert; Gopal Gandham; Milos Hrkic; Jiang Hu; Stephen T. Quay; Cliff C. N. Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Closed-form delay and slew metrics made easy. - Charles J. Alpert; Frank Liu 001; Chandramouli V. Kashyap; Anirudh Devgan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. - Chandramouli V. Kashyap; Charles J. Alpert; Frank Liu 001; Anirudh Devgan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A delay metric for RC circuits based on the Weibull distribution. - Frank Liu 001; Chandramouli V. Kashyap; Charles J. Alpert (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Placement stability metrics. - Charles J. Alpert; Gi-Joon Nam; Paul Villarribua; Mehmet Can Yildiz (ASP-DAC, 2005)

Making fast buffer insertion even faster via approximation techniques. - Zhuo Li 001; Cliff C. N. Sze; Charles J. Alpert; Jiang Hu; Weiping Shi (ASP-DAC, 2005)

Diffusion-based placement migration. - Haoxing Ren; David Zhigang Pan; Charles J. Alpert; Paul Villarrubia (DAC, 2005)

Computational geometry based placement migration. - Tao Luo 002; Haoxing Ren; Charles J. Alpert; David Zhigang Pan (ICCAD, 2005)

Practical techniques to reduce skew and its variations in buffered clock networks. - Ganesh Venkataraman; Nikhil Jayakumar; Jiang Hu; Peng Li 001; Sunil P. Khatri; Anand Rajaram; Patrick McGuinness; Charles J. Alpert (ICCAD, 2005)

A semi-persistent clustering technique for VLSI circuit placement. - Charles J. Alpert; Andrew B. Kahng; Gi-Joon Nam; Sherief Reda; Paul Villarrubia (ISPD, 2005)

The ISPD2005 placement contest and benchmark suite. - Gi-Joon Nam; Charles J. Alpert; Paul Villarrubia; Bruce Winter; Mehmet Can Yildiz (ISPD, 2005)

An efficient surface-based low-power buffer insertion algorithm. - Rajeev R. Rao; David T. Blaauw; Dennis Sylvester; Charles J. Alpert; Sani R. Nassif (ISPD, 2005)

Timing-driven Steiner trees are (practically) free. - Charles J. Alpert; Andrew B. Kahng; Cliff C. N. Sze; Qinke Wang (DAC, 2006)

Accurate estimation of global buffer delay within a floorplan. - Charles J. Alpert; Jiang Hu; Sachin S. Sapatnekar; Cliff C. N. Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A Fast Hierarchical Quadratic Placement Algorithm. - Gi-Joon Nam; Sherief Reda; Charles J. Alpert; Paul Villarrubia; Andrew B. Kahng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

ISPD 2005/2006 Placement Benchmarks. - Gi-Joon Nam; Charles J. Alpert; Paul G. Villarrubia (Modern Circuit Placement, 2007)

Fast Electrical Correction Using Resizing and Buffering. - Shrirang K. Karandikar; Charles J. Alpert; Mehmet Can Yildiz; Paul Villarrubia; Stephen T. Quay; T. Mahmud (ASP-DAC, 2007)

Hippocrates: First-Do-No-Harm Detailed Placement. - Haoxing Ren; David Z. Pan; Charles J. Alpert; Gi-Joon Nam; Paul G. Villarrubia (ASP-DAC, 2007)

RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. - Natarajan Viswanathan; Gi-Joon Nam; Charles J. Alpert; Paul Villarrubia; Haoxing Ren; Chris C. N. Chu (DAC, 2007)

The coming of age of physical synthesis. - Charles J. Alpert; Chris C. N. Chu; Paul G. Villarrubia (ICCAD, 2007)

Probabilistic Congestion Prediction with Partial Blockages. - Zhuo Li 001; Charles J. Alpert; Stephen T. Quay; Sachin S. Sapatnekar; Weiping Shi (ISQED, 2007)

The nuts and bolts of physical synthesis. - Charles J. Alpert; Shrirang K. Karandikar; Zhuo Li 001; Gi-Joon Nam; Stephen T. Quay; Haoxing Ren; Cliff C. N. Sze; Paul G. Villarrubia; Mehmet Can Yildiz (SLIP, 2007)

Techniques for Fast Physical Synthesis. - Charles J. Alpert; Shrirang K. Karandikar; Zhuo Li 001; Gi-Joon Nam; Stephen T. Quay; Haoxing Ren; Cliff C. N. Sze; Paul G. Villarrubia; Mehmet Can Yildiz (Proc. IEEE, 2007)

Fast Algorithms for Slew-Constrained Minimum Cost Buffering. - Shiyan Hu 001; Charles J. Alpert; Jiang Hu; Shrirang K. Karandikar; Zhuo Li 001; Weiping Shi; Chin Ngai Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Diffusion-Based Placement Migration With Application on Legalization. - Haoxing Ren; David Z. Pan; Charles J. Alpert; Paul G. Villarrubia; Gi-Joon Nam (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Path-Based Buffer Insertion. - Chin Ngai Sze; Charles J. Alpert; Jiang Hu; Weiping Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Path smoothing via discrete optimization. - Michael D. Moffitt; David A. Papa; Zhuo Li 001; Charles J. Alpert (DAC, 2008)

A polynomial time approximation scheme for timing constrained minimum cost layer assignment. - Shiyan Hu 001; Zhuo Li 001; Charles J. Alpert (ICCAD, 2008)

Pyramids: an efficient computational geometry-based approach for timing-driven placement. - Tao Luo 002; David A. Papa; Zhuo Li 001; Chin Ngai Sze; Charles J. Alpert; David Z. Pan (ICCAD, 2008)

Fast interconnect synthesis with layer assignment. - Zhuo Li 001; Charles J. Alpert; Shiyan Hu 001; Tuhin Muhmud; Stephen T. Quay; Paul G. Villarrubia (ISPD, 2008)

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. - David A. Papa; Tao Luo 002; Michael D. Moffitt; Chin Ngai Sze; Zhuo Li 001; Gi-Joon Nam; Charles J. Alpert; Igor L. Markov (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Placement-Driven Synthesis Design Closure Tool. - Charles J. Alpert; Nathaniel Hieter; Arjen Mets; Ruchir Puri; Lakshmi N. Reddy; Haoxing Ren; Louise Trevillyan (Handbook of Algorithms for Physical Design Automation, 2008)

Introduction to Physical Design. - Charles J. Alpert; Dinesh P. Mehta; Sachin S. Sapatnekar (Handbook of Algorithms for Physical Design Automation, 2008)

A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. - Shiyan Hu 001; Zhuo Li 001; Charles J. Alpert (DAC, 2009)

CRISP: Congestion reduction by iterated spreading during placement. - Jarrod A. Roy; Natarajan Viswanathan; Gi-Joon Nam; Charles J. Alpert; Igor L. Markov (ICCAD, 2009)

A faster approximation scheme for timing driven minimum cost layer assignment. - Shiyan Hu 001; Zhuo Li 001; Charles J. Alpert (ISPD, 2009)

Ispd2009 clock network synthesis contest. - Cliff N. Sze; Phillip J. Restle; Gi-Joon Nam; Charles J. Alpert (ISPD, 2009)

A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment. - Shiyan Hu 001; Zhuo Li 001; Charles J. Alpert (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Detecting tangled logic structures in VLSI netlists. - Tanuj Jindal; Charles J. Alpert; Jiang Hu; Zhuo Li 001; Gi-Joon Nam; Charles B. Winn (DAC, 2010)

Design-hierarchy aware mixed-size placement for routability optimization. - Yi-Lin Chuang; Gi-Joon Nam; Charles J. Alpert; Yao-Wen Chang; Jarrod A. Roy; Natarajan Viswanathan (ICCAD, 2010)

New placement prediction and mitigation techniques for local routing congestion. - Taraneh Taghavi; Zhuo Li 001; Charles J. Alpert; Gi-Joon Nam; Andrew D. Huber; Shyam Ramji (ICCAD, 2010)

What makes a design difficult to route. - Charles J. Alpert; Zhuo Li 001; Michael D. Moffitt; Gi-Joon Nam; Jarrod A. Roy; Gustavo E. Téllez (ISPD, 2010)

Ultra-fast interconnect driven cell cloning for minimizing critical path delay. - Zhuo Li 001; David A. Papa; Charles J. Alpert; Shiyan Hu 001; Weiping Shi; Cliff C. N. Sze; Nancy Ying Zhou (ISPD, 2010)

ITOP: integrating timing optimization within placement. - Natarajan Viswanathan; Gi-Joon Nam; Jarrod A. Roy; Zhuo Li 001; Charles J. Alpert; Shyam Ramji; Chris Chu (ISPD, 2010)

Speeding Up Physical Synthesis with Transactional Timing Analysis. - David A. Papa; Michael D. Moffitt; Charles J. Alpert; Igor L. Markov (IEEE Des. Test Comput., 2010)

The ISPD-2011 routability-driven placement contest and benchmark suite. - Natarajan Viswanathan; Charles J. Alpert; Cliff C. N. Sze; Zhuo Li 001; Gi-Joon Nam; Jarrod A. Roy (ISPD, 2011)

Quantifying academic placer performance on custom designs. - Samuel I. Ward; David A. Papa; Zhuo Li 001; Cliff N. Sze; Charles J. Alpert; Earl E. Swartzlander Jr. (ISPD, 2011)

Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. - David A. Papa; Charles J. Alpert; Cliff C. N. Sze; Zhuo Li 001; Natarajan Viswanathan; Gi-Joon Nam; Igor L. Markov (IEEE Micro, 2011)

Shedding Physical Synthesis Area Bloat. - Nancy Ying Zhou; Charles J. Alpert; Zhuo Li 001; Cliff N. Sze; Louise Trevillyan (VLSI Design, 2011)

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. - Zhuo Li 001; Charles J. Alpert; Gi-Joon Nam; Cliff C. N. Sze; Natarajan Viswanathan; Nancy Y. Zhou (DAC, 2012)

The DAC 2012 routability-driven placement contest and benchmark suite. - Natarajan Viswanathan; Charles J. Alpert; Cliff C. N. Sze; Zhuo Li 001; Yaoguang Wei (DAC, 2012)

GLARE: global and local wiring aware routability evaluation. - Yaoguang Wei; Cliff C. N. Sze; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Lakshmi N. Reddy; Andrew D. Huber; Gustavo E. Téllez; Douglas Keller; Sachin S. Sapatnekar (DAC, 2012)

WRIP: logic restructuring techniques for wirelength-driven incremental placement. - Xing Wei; Wai-Chung Tang; Yu-Liang Wu; Cliff C. N. Sze; Charles J. Alpert (ACM Great Lakes Symposium on VLSI, 2012)

Placement: Hot or Not? - Charles J. Alpert; Zhuo Li 001; Gi-Joon Nam; Chin Ngai Sze; Natarajan Viswanathan; Samuel I. Ward (ICCAD, 2012)

ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. - Natarajan Viswanathan; Charles J. Alpert; Cliff C. N. Sze; Zhuo Li 001; Yaoguang Wei (ICCAD, 2012)

MAPLE: multilevel adaptive placement for mixed-size designs. - Myung-Chul Kim; Natarajan Viswanathan; Charles J. Alpert; Igor L. Markov; Shyam Ramji (ISPD, 2012)

Keep it straight: teaching placement how to better handle designs with datapaths. - Samuel I. Ward; Myung-Chul Kim; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Earl E. Swartzlander Jr.; David Z. Pan (ISPD, 2012)

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. - Xing Wei; Wai-Chung Tang; Yu-Liang Wu; Cliff C. N. Sze; Charles J. Alpert (ASP-DAC, 2013)

Routing congestion estimation with real design constraints. - Wen-Hao Liu 001; Yaoguang Wei; Cliff C. N. Sze; Charles J. Alpert; Zhuo Li 001; Yih-Lang Li; Natarajan Viswanathan (DAC, 2013)

CATALYST: planning layer directives for effective design closure. - Yaoguang Wei; Zhuo Li 001; Cliff C. N. Sze; Shiyan Hu 001; Charles J. Alpert; Sachin S. Sapatnekar (DATE, 2013)

ICCAD-2013 CAD contest in placement finishing and benchmark suite. - Myung-Chul Kim; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert (ICCAD, 2013)

Clock power minimization using structured latch templates and decision tree induction. - Samuel I. Ward; Natarajan Viswanathan; Nancy Y. Zhou; Cliff C. N. Sze; Zhuo Li 001; Charles J. Alpert; David Z. Pan (ICCAD, 2013)

Structure-Aware Placement Techniques for Designs With Datapaths. - Samuel I. Ward; Myung-Chul Kim; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Earl E. Swartzlander Jr.; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Pacman: driving nonuniform clock grid loads for low-skew robust clock network. - Nancy Y. Zhou; Phillip J. Restle; Joseph N. Palumbo; Joseph N. Kozhaya; Haifeng Qian; Zhuo Li 001; Charles J. Alpert; Cliff C. N. Sze (SLIP, 2014)

Techniques for scalable and effective routability evaluation. - Yaoguang Wei; Cliff C. N. Sze; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Lakshmi N. Reddy; Andrew D. Huber; Gustavo E. Téllez; Douglas Keller; Sachin S. Sapatnekar (ACM Trans. Design Autom. Electr. Syst., 2014)

Editorial. - Vijaykrishnan Narayanan; Charles J. Alpert; Sara Dailey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. - Bei Yu 001; Xiaoqing Xu; Jhih-Rong Gao; Yibo Lin; Zhuo Li 001; Charles J. Alpert; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Modern Challenges in Constructing Clocks. - Charles J. Alpert (ISPD, 2017)

Stitch aware detailed placement for multiple E-beam lithography. - Yibo Lin; Bei Yu 001; Yi Zou; Zhuo Li 001; Charles J. Alpert; David Z. Pan (Integr., 2017)

Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. - Charles J. Alpert; Wing-Kai Chow; Kwangsoo Han; Andrew B. Kahng; Zhuo Li 001; Derong Liu 002; Sriram Venkatesh (ISPD, 2018)

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. - Yibo Lin; Bei Yu 001; Xiaoqing Xu; Jhih-Rong Gao; Natarajan Viswanathan; Wen-Hao Liu 001; Zhuo Li 001; Charles J. Alpert; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)