A Systematic Approach for Designing Testable VLSI Circuits. - Sen-Pin Lin; Charles Njinda; Melvin A. Breuer (ICCAD, 1991)

Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware. - Debaditya Mukherjee; Charles Njinda; Melvin A. Breuer (ICCAD, 1991)

A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing. - Rajagopalan Srinivasan; Charles Njinda; Melvin A. Breuer (VTS, 1991)

SIESTA: a multi-facet scan design system. - Sridhar Narayanan; Charles Njinda; Rajesh Gupta 003; Melvin A. Breuer (EURO-DAC, 1992)

Optimal Sequencing of Scan Registers. - Sridhar Narayanan; Charles Njinda; Melvin A. Breuer (ITC, 1992)

Generating a family of testable designs using the BILBO methodology. - Sen-Pin Lin; Charles Njinda; Melvin A. Breuer (J. Electron. Test., 1993)

Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. - Ishwar Parulkar; Melvin A. Breuer; Charles Njinda (DAC, 1994)

SWiTEST: a switch level test generation system for CMOS combinational circuits. - Kuen-Jong Lee; Charles Njinda; Melvin A. Breuer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Performance Driven BIST Technique for Random Logic. - Charles Njinda; Neeraj Kaul (ITC, 1995)

Efficient Testing of Clock Regenerator Circuits in Scan Designs. - Rajesh Raina; Robert Bailey; Charles Njinda; Robert F. Molyneaux; Charlie Beh (DAC, 1997)

How Seriously Do You Take Your Possible-Detect Faults? - Rajesh Raina; Charles Njinda; Robert F. Molyneaux (ITC, 1997)

A Hierarchical DFT Architecture for Chip, Board and System Test/Debug. - Charles Njinda (ITC, 2004)