Wire planning for performance and yield enhancement. - Charles Ouyang; Kyungsuk Ryu; Hans T. Heineken; Jitu Khare; Saghir A. Shaikh; Manuel d'Abreu (CICC, 2000)

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. - Visvesh S. Sathe 001; Srikanth Arekapudi; Alexander T. Ishii; Charles Ouyang; Marios C. Papaefthymiou; Samuel Naffziger (IEEE J. Solid State Circuits, 2013)