Compilation-based prefetching for memory latency tolerance. - Charles Selvidge (1992)

TIERS: Topology Independent Pipelined Routing and Scheduling for VirtualWire Compilation. - Charles Selvidge; Anant Agarwal; Matthew Dahl; Jonathan Babb (FPGA, 1995)

A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification. - Murali Kudlugi; Soha Hassoun; Charles Selvidge; Duaine Pryor (DAC, 2001)

Static Scheduling of Multiple Asynchronous Domains For Functional Verification. - Murali Kudlugi; Charles Selvidge; Russell Tessier (DAC, 2001)

Static Scheduling of Multi-Domain Memories For Functional Verification. - Murali Kudlugi; Charles Selvidge; Russell Tessier (ICCAD, 2001)

Acyclic modeling of combinational loops. - Amit Gupta; Charles Selvidge (ICCAD, 2005)

A transaction-based unified architecture for simulation and emulation. - Soha Hassoun; Murali Kudlugi; Duaine Pryor; Charles Selvidge (IEEE Trans. Very Large Scale Integr. Syst., 2005)