Matching considerations in I/Q A/D converter pairs. - Charles T. Peach; Waisiu Law; D. R. Beck; Ward J. Helms; David J. Allstot (ISCAS (3), 2002)

A mixed-signal calibration technique for low-voltage CMOS 1.5-bit/stage pipeline data converters. - Jianjun Guo; Waisiu Law; Charles T. Peach; Ward J. Helms; David J. Allstot (ISCAS (1), 2003)

A monotonic digital calibration technique for pipelined data converters. - Waisiu Law; Jianjun Guo; Charles T. Peach; Ward J. Helms; David J. Allstot (ISCAS (1), 2003)

A 9-b 400 Msample/s pipelined analog-to digital converter in 90nm CMOS. - Charles T. Peach; Ashoke Ravi; Rosie Bishop; Krishnamurthy Soumyanath; David J. Allstot (ESSCIRC, 2005)

An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 μ m CMOS. - Charles T. Peach; Un-Ku Moon; David J. Allstot (IEEE J. Solid State Circuits, 2010)