A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. - John Barth 001; William R. Reohr; Paul C. Parries; Gregory Fredeman; John Golz; Stanley Schuster; Richard E. Matick; Hillery C. Hunter; Charles Tanner; Joseph Harig; Hoki Kim; Babar A. Khan; et al. (ISSCC, 2007)

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. - John Barth 001; William R. Reohr; Paul C. Parries; Gregory Fredeman; John Golz; Stanley Schuster; Richard E. Matick; Hillery C. Hunter; Charles Tanner; Joseph Harig; Hoki Kim; Babar A. Khan; et al. (IEEE J. Solid State Circuits, 2008)