A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. - Charlie Brej; Jim D. Garside (VLSI Design, 2005)

Self-timed full adder designs based on hybrid input encoding. - P. Balasubramanian 001; David A. Edwards; Charlie Brej (DDECS, 2009)

Forward and backward guarding in early output logic. - Charlie Brej; Doug Edwards (DDECS, 2009)

Wagging Logic: Implicit Parallelism Extraction Using Asynchronous Methodologies. - Charlie Brej (ACSD, 2010)