Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. - Chung-Ping Chen; Yao-Wen Chang; D. F. Wong 001 (DAC, 1996)

Optimal Wire-Sizing Formular Under the Elmore Delay Model. - Chung-Ping Chen; Yao-Ping Chen; D. F. Wong 001 (DAC, 1996)

Optimal non-uniform wire-sizing under the Elmore delay model. - Chung-Ping Chen; Hai Zhou 001; D. F. Wong 001 (ICCAD, 1996)

Optimal Wire-Sizing Function with Fringing Capacitance Consideration. - Chung-Ping Chen; D. F. Wong 001 (DAC, 1997)

Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching. - Chung-Ping Chen; Noel Menezes (DAC, 1999)

Error Bounded Padé Approximation via Bilinear Conformal Transformation. - Chung-Ping Chen; D. F. Wong 001 (DAC, 1999)

Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. - Noel Menezes; Chung-Ping Chen (VLSI Design, 1999)

Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. - Chung-Ping Chen; Chris C. N. Chu; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's Equations Solver for VLSI Interconnect Modeling. - Charlie Chung-Ping Chen; Tae-Woo Lee; Narayanan Murugesan; Susan C. Hagness (ICCAD, 2000)

Optimal spacing and capacitance padding for general clock structures. - Yu-Min Lee; Hing Yin Lai; Charlie Chung-Ping Chen (ASP-DAC, 2001)

Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods. - Tsung-Hao Chen; Charlie Chung-Ping Chen (DAC, 2001)

Hierarchical model order reduction for signal-integrity interconnect synthesis. - Yu-Min Lee; Charlie Chung-Ping Chen (ACM Great Lakes Symposium on VLSI, 2001)

Linear Time Hierarchical Capacitance Extraction without Multipole Expansion. - Saisanthosh Balakrishnan; Jong Hyuk Park; Hyungsuk Kim; Yu-Min Lee; Charlie Chung-Ping Chen (ICCD, 2001)

RC-in RC-out Model Order Reduction Accurate up to Second Order Moments. - Pradeepsunder Ganesh; Charlie Chung-Ping Chen (ICCD, 2001)

HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery. - Yahong Cao; Yu-Min Lee; Tsung-Hao Chen; Charlie Chung-Ping Chen (DAC, 2002)

INDUCTWISE: inductance-wise interconnect simulator and extractor. - Tsung-Hao Chen; Clement Luk; Hyungsuk Kim; Charlie Chung-Ping Chen (ICCAD, 2002)

Future SoC Design Challenges and Solutions (invited). - Charlie Chung-Ping Chen; Ed Cheng (ISQED, 2002)

Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm. - Ting-Yuan Wang; Charlie Chung-Ping Chen (ISQED, 2002)

Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method. - Yu-Min Lee; Charlie Chung-Ping Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

3-D Thermal-ADI: a linear-time chip level transient thermal simulator. - Ting-Yuan Wang; Charlie Chung-Ping Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation. - Yu-Min Lee; Charlie Chung-Ping Chen; Yao-Wen Chang; Martin D. F. Wong (VLSI Design, 2002)

A hierarchical analysis methodology for chip-level power delivery with realizable model reduction. - Yu-Min Lee; Charlie Chung-Ping Chen (ASP-DAC, 2003)

The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method . - Yu-Min Lee; Charlie Chung-Ping Chen (DATE, 2003)

SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation. - Tsung-Hao Chen; Clement Luk; Charlie Chung-Ping Chen (ICCAD, 2003)

PODEA: Power delivery efficient analysis with realizable model reduction. - Rong Jiang 002; Tsung-Hao Chen; Charlie Chung-Ping Chen (ISCAS (4), 2003)

Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. - Jeng-Liang Tsai; Tsung-Hao Chen; Charlie Chung-Ping Chen (ISPD, 2003)

3D thermal-ADI: an efficient chip-level transient thermal simulator. - Ting-Yuan Wang; Yu-Min Lee; Charlie Chung-Ping Chen (ISPD, 2003)

INDUCTWISE: inductance-wise interconnect simulator and extractor. - Tsung-Hao Chen; Clement Luk; Charlie Chung-Ping Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method. - Yu-Min Lee; Charlie Chung-Ping Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Thermal-ADI - a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method. - Ting-Yuan Wang; Charlie Chung-Ping Chen (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Frequency-dependent reluctance extraction. - Clement Luk; Tsung-Hao Chen; Charlie Chung-Ping Chen (ASP-DAC, 2004)

EPEEC: a compact reluctance based interconnect model considering lossy substrate eddy currents. - Rong Jiang 002; Charlie Chung-Ping Chen (CICC, 2004)

Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining. - Lizheng Zhang; Yuhen Hu; Charlie Chung-Ping Chen (DAC, 2004)

SCORE: SPICE COmpatible Reluctance Extraction. - Rong Jiang 002; Charlie Chung-Ping Chen (DATE, 2004)

Realizable Reduction for Electromagnetically Coupled RLMC Interconnects. - Rong Jiang 002; Charlie Chung-Ping Chen (DATE, 2004)

Thermal and Power Integrity Based Power/Ground Networks Optimization. - Ting-Yuan Wang; Jeng-Liang Tsai; Charlie Chung-Ping Chen (DATE, 2004)

A yield improvement methodology using pre- and post-silicon statistical clock scheduling. - Jeng-Liang Tsai; Dong Hyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja (ICCAD, 2004)

Sensitivity guided net weighting for placement driven synthesis. - Ting-Yuan Wang; Jeng-Liang Tsai; Charlie Chung-Ping Chen (ISPD, 2004)

SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis Based on Modeling Order Reduction. - Ting-Yuan Wang; Charlie Chung-Ping Chen (ISQED, 2004)

Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. - Jeng-Liang Tsai; Tsung-Hao Chen; Charlie Chung-Ping Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation. - Hsinwei Chou; Yu-Hao Wang; Charlie Chung-Ping Chen (ASP-DAC, 2005)

Comprehensive frequency dependent interconnect extraction and evaluation methodology. - Rong Jiang 002; Charlie Chung-Ping Chen (ASP-DAC, 2005)

Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. - Jeng-Liang Tsai; Charlie Chung-Ping Chen (ASP-DAC, 2005)

Wave-pipelined on-chip global interconnect. - Lizheng Zhang; Yuhen Hu; Charlie Chung-Ping Chen (ASP-DAC, 2005)

Block based statistical timing analysis with extended canonical timing model. - Lizheng Zhang; Yuhen Hu; Charlie Chung-Ping Chen (ASP-DAC, 2005)

ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction. - Rong Jiang 002; Yi-Hao Chang; Charlie Chung-Ping Chen (DAC, 2005)

Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model. - Lizheng Zhang; Weijen Chen; Yuhen Hu; John A. Gubner; Charlie Chung-Ping Chen (DAC, 2005)

Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model. - Lizheng Zhang; Weijen Chen; Yuhen Hu; Charlie Chung-Ping Chen (DATE, 2005)

1-V 7-mW dual-band fast-locked frequency synthesizer. - Vikas Sharma; Chien-Liang Chen; Chung-Ping Chen (ACM Great Lakes Symposium on VLSI, 2005)

Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. - Rong Jiang 002; Wenyin Fu; Janet Meiling Wang; Vince Lin; Charlie Chung-Ping Chen (ICCAD, 2005)

System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS). - Janet Meiling Wang; Bharat Srinivas; Dongsheng Ma; Charlie Chung-Ping Chen; Jun Li 066 (ICCAD, 2005)

False Path and Clock Scheduling Based Yield-Aware Gate Sizing. - Jeng-Liang Tsai; Dong Hyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja (VLSI Design, 2005)

Yield-Driven, False-Path-Aware Clock Skew Scheduling. - Jeng-Liang Tsai; Dong Hyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja (IEEE Des. Test Comput., 2005)

EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates. - Rong Jiang 002; Wenyin Fu; Charlie Chung-Ping Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery. - Yu-Min Lee; Yahong Cao; Tsung-Hao Chen; Janet Meiling Wang; Charlie Chung-Ping Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. - Lizheng Zhang; Jeng-Liang Tsai; Weijen Chen; Yuhen Hu; Charlie Chung-Ping Chen (ASP-DAC, 2006)

Statistical timing analysis with path reconvergence and spatial correlations. - Lizheng Zhang; Yuhen Hu; Charlie Chung-Ping Chen (DATE, 2006)

Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method. - Pei-Yu Huang; Yu-Min Lee; Jeng-Liang Tsai; Charlie Chung-Ping Chen (ISCAS, 2006)

Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis. - Lizheng Zhang; Jun Shao; Charlie Chung-Ping Chen (ISPD, 2006)

ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems. - Sanghamitra Roy; Charlie Chung-Ping Chen (ISQED, 2006)

Temperature-Aware Placement for SOCs. - Jeng-Liang Tsai; Charlie Chung-Ping Chen; Guoqiang Chen; Brent Goplen; Haifeng Qian; Yong Zhan; Sung-Mo Kang; Martin D. F. Wong; Sachin S. Sapatnekar (Proc. IEEE, 2006)

Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model. - Lizheng Zhang; Weijen Chen; Yuhen Hu; Charlie Chung-Ping Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables. - Lizheng Zhang; Weijen Chen; Yuhen Hu; John A. Gubner; Charlie Chung-Ping Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design. - Sanghamitra Roy; Charlie Chung-Ping Chen (ASP-DAC, 2007)

3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method. - Dongkeun Oh; Charlie Chung-Ping Chen; Yu Hen Hu (ISQED, 2007)

Numerically Convex Forms and Their Application in Gate Sizing. - Sanghamitra Roy; Weijen Chen; Charlie Chung-Ping Chen; Yu Hen Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

LTCC spiral inductor modeling, synthesis, and optimization. - Tuck Boon Chan; Hsinchia Lu; Jun-Kuei Zeng; Charlie Chung-Ping Chen (ASP-DAC, 2008)

An optimal algorithm for sizing sequential circuits for industrial library based designs. - Sanghamitra Roy; Yu Hen Hu; Charlie Chung-Ping Chen; Shih-Pin Hung; Tse-Yu Chiang; Jiuan-Guei Tseng (ASP-DAC, 2008)

Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications. - Jui-Hsiang Liu; Ming-Feng Tsai; Lumdo Chen; Charlie Chung-Ping Chen (DAC, 2008)

Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis. - Jun-Kuei Zeng; Chung-Ping Chen (DATE, 2008)

Process-Variation Statistical Modeling for VLSI Timing Analysis. - Jui-Hsiang Liu; Jun-Kuei Zeng; Ai-Syuan Hong; Lumdo Chen; Charlie Chung-Ping Chen (ISQED, 2008)

Performance measurement and queueing analysis of medium-high blocking probability of two and three parallel connection servers. - Chung-Ping Chen; Ying-Wen Bai; Yin-Sheng Lee (LCN, 2008)

Wire Sizing. - Sanghamitra Roy; Charlie Chung-Ping Chen (Handbook of Algorithms for Physical Design Automation, 2008)

Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors. - Dongkeun Oh; Nam Sung Kim; Charlie Chung-Ping Chen; Azadeh Davoodi; Yu Hen Hu (ASP-DAC, 2010)

Interconnect delay and slew metrics using the beta distribution. - Jun-Kuei Zeng; Chung-Ping Chen (DATE, 2010)

The compatibility analysis of thread migration and DVFS in multi-core processor. - Dongkeun Oh; Charlie Chung-Ping Chen; Nam Sung Kim; Yu Hen Hu (ISQED, 2010)

Interconnect delay and slew metrics using the extreme value distribution. - Jun-Kuei Zeng; Chung-Ping Chen (ISQED, 2010)

Accurate and Analytical Statistical Spatial Correlation Modeling Based on Singular Value Decomposition for VLSI DFM Applications. - Jui-Hsiang Liu; Ming-Feng Tsai; Lumdo Chen; Charlie Chung-Ping Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Epileptic Seizure Detection for Multichannel EEG Signals with Support Vector Machines. - Chia-Ping Shen; Chih-Min Chan; Feng-Sheng Lin; Ming-Jang Chiu; Jeng-Wei Lin; Jui-Hung Kao; Chung-Ping Chen; Feipei Lai (BIBE, 2011)

An at-speed self-testable technique for the high speed domino adder. - Yu-Shun Wang; Min-Han Hsieh; Chia-Ming Liu; Chi-Wei Liu; James Chien-Mo Li; Charlie Chung-Ping Chen (CICC, 2011)

A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique. - Yu-Shun Wang; Min-Han Hsieh; Chia-Ming Liu; Yi-Chi Wu; Bing-Feng Lin; Hsien-Chen Chiu; Charlie Chung-Ping Chen (ISCAS, 2011)

A 12 Gb/s chip-to-chip AC coupled transceiver. - Yu-Shun Wang; Min-Han Hsieh; Yi-Chi Wu; Chia-Ming Liu; Hsien-Chen Chiu; Bing-Feng Lin; Charlie Chung-Ping Chen (ISCAS, 2011)

Equivalent bandwidth model of parallel servers with a variation of CPU loads, system response time and number of users. - Chung-Ping Chen; Ying-Wen Bai; Hsiang-Hsiu Peng (CCECE, 2012)

A 2 - 8 GHz multi-phase distributed DLL using phase insertion in 90 nm. - Min-Han Hsieh; Bing-Feng Lin; Yu-Shun Wang; Hao-Huei Chang; Charlie Chung-Ping Chen (ISCAS, 2012)

A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS. - Min-Han Hsieh; Liang-Hsin Chen; Shen-Iuan Liu; Charlie Chung-Ping Chen (ISSCC, 2012)

Efficient Thermal Simulation for 3-D IC With Thermal Through-Silicon Vias. - Dongkeun Oh; Charlie Chung-Ping Chen; Yu Hen Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example. - Yu-Shun Wang; Min-Han Hsieh; James Chien-Mo Li; Charlie Chung-Ping Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS. - Wei-Sheng Cheng; Min-Han Hsieh; Shuo-Hong Hung; Szu-Yao Hung; Charlie Chung-Ping Chen (ISCAS, 2013)

A high dynamic range programmable gain amplifier for HomePlug AV powerline communication system. - Szu-Yao Hung; Kai-Hsiang Chan; Charlie Chung-Ping Chen (ISCAS, 2013)

A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology. - Pang-Kai Liu; Szu-Yao Hung; Chang-Yi Liu; Min-Han Hsieh; Charlie Chung-Ping Chen (ISCAS, 2013)

Cost-efficient hardware implementation of stereo image depth optimization system. - Chun-Chang Yu; Chia-Hao Cheng; Pei-Chun Lin; Charlie Chung-Ping Chen (IC3D, 2014)

An efficient multi-touch tracking algorithm with a large number of points. - Shih-Lun Huang; Sheng-Yi Hung; Charlie Chung-Ping Chen; Cheng-Han Tsao; Nai-Wen Chang 005 (ICCE-Berlin, 2014)

Current-mode adaptively hysteretic control for buck converters with fast transient response and improved output regulation. - Kuan-I Wu; Shuo-Hong Hung; Shang-Yu Shieh; Bor-Tsang Hwang; Szu-Yao Hung; Charlie Chung-Ping Chen (ISCAS, 2014)

Clustering-based multi-touch algorithm framework for the tracking problem with a large number of points. - Shih-Lun Huang; Sheng-Yi Hung; Chung-Ping Chen (DATE, 2015)

Bandwidth performance analysis with a variation of Webpage sizes. - Chung-Ping Chen; Guan-Jhong Lin; Yen-Hsemg Lin; Huai-Ping Song (ICMLC, 2015)

A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme. - Ai Chien; Shuo-Hong Hung; Kuan-I Wu; Chang-Yi Liu; Min-Han Hsieh; Charlie Chung-Ping Chen (ISCAS, 2015)

A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique. - Shuo-Hong Hung; Wei-Hao Kao; Kuan-I Wu; Yi-Wei Huang; Min-Han Hsieh; Charlie Chung-Ping Chen (ISCAS, 2015)

A fast-settling high linearity auto gain control for broadband OFDM-based PLC system. - Kuan-I Wu; Szu-Yao Hung; Shuo-Hong Hung; Charlie Chung-Ping Chen (ISCAS, 2015)

A -194 dBc/Hz FOM interactive current-reused QVCO (ICR-QVCO) with capacitor-coupling self-switching sinusoidal current biasing (CSSCB) phase noise reduction technique. - Kuan-I Wu; I-Shing Shen; Christina F. Jou; Charlie Chung-Ping Chen (VLSIC, 2015)

Lossless compression algorithm based on dictionary coding for multiple e-beam direct write system. - Pei-Chun Lin; Yu-Hsuan Pai; Yu-Hsiang Chiu; Shao-Yuan Fang; Charlie Chung-Ping Chen (DATE, 2016)

A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS. - Min-Han Hsieh; Liang-Hsin Chen; Shen-Iuan Liu; Charlie Chung-Ping Chen (IEEE J. Solid State Circuits, 2016)

An efficient DFT-based algoritiim for the charger noise problem in capacitive touch applications. - Shih-Lun Huang; Sheng-Yi Hung; Chung-Ping Chen (ISCAS, 2017)

A Real Time EEG Analysis System for the Prediction of Clinical Antidepressant Responses. - Shuo-Hong Hung; Ina Wu; Yi-Chen Li 002; Cheng-Ta Li; Charlie Chung-Ping Chen (DSP, 2018)

Subjective Interpupillary Distance of Measurement Technique. - Jih-Yi Liao; Der-Chin Chen; Shih-Tsung Chang; Chung-Ping Chen; Chao-Han Wu; Cheng-Ke Hsu (ISPACS, 2019)

Frequency Hopping and Parallel Driving With Random Delay Especially Suitable for the Charger Noise Problem in Mutual-Capacitive Touch Applications. - Shih-Lun Huang; Sheng-Yi Hung; Chung-Ping Chen (IEEE Access, 2019)

A Transient Enhancement DC-DC Buck Converter With Dual Operating Modes Control Technique. - Yi-Chieh Hsu; Chung-Yi Ting; Li-Sheng Hsu; Jing-Yuan Lin; Charlie Chung-Ping Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jiun-Lang Huang; Chung-Ping Chen (ICCAD, 2020)

A Quasi-V2 Hysteretic Buck Converter With Adaptive COT Control for Fast DVS and Load-Transient Response in RF Applications. - Chung-Yi Ting; Jing-Yuan Lin; Charlie Chung-Ping Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup. - Chun-Chang Yu; Yu Hen Hu; Yi-Chang Lu; Charlie Chung-Ping Chen (DATE, 2021)

Opportunities for 2.5/3D Heterogeneous SoC Integration. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jiun-Lang Huang; Chung-Ping Chen (VLSI-DAT, 2021)

Intelligent Design Automation for Heterogeneous Integration. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jiun-Lang Huang; Charlie Chung-Ping Chen (ISPD, 2022)

A Ripple-Based Constant On-Time Controlled DC-DC Buck Converter with Inductor Current Sensing Technique. - Sheng-Jen Cheng; Chieh-Ju Tsai; Sheng-Yu Wang; Wei-Yi Liu; Chung-Ping Chen (ISCAS, 2023)

Injection-Locked Frequency Sixtuplers in 90 nm CMOS by Using the Push-Push Doubler. - Sheng-Jen Cheng; Pi-Neng Shen; Chung-Hung Hong; Zheng-Wei Chen; Chung-Ping Chen; Sheng-Lyang Jang (IEEE Access, 2023)

Transformer Based Real Time Musculoskeletal Anatomical Structure Detection in Clinical Use. - Jyun-Ping Kao; Hao-Yu Hung; Ping-Xuan Chen; Chung-Ping Chen; Wen-Shiang Chen (BIBE, 2024)