Identification of DRAM sense-amplifier imbalance using hot-carrier evaluation. - S. Aur; Charvaka Duvvury; Hugh McAdams; C. Perrin (IEEE J. Solid State Circuits, 1992)

Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices. - Carlos H. Díaz; Charvaka Duvvury; Sung-Mo Kang (ISCAS, 1993)

ESD: a pervasive reliability concern for IC technologies. - Charvaka Duvvury; Ajith Amerasekera (Proc. IEEE, 1993)

Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices. - Carlos H. Díaz; Sung-Mo Kang; Charvaka Duvvury (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

ESD: Design For IC Chip Quality and Reliability. - Charvaka Duvvury (ISQED, 2000)

ESD protection device issues for IC designs. - Charvaka Duvvury (CICC, 2001)

Issues in Deep Submicron State-of-the-Art ESD Design. - Charvaka Duvvury (ISQED, 2001)

A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies. - Steven H. Voldman; W. Anderson; R. Ashton; M. Chaine; Charvaka Duvvury; T. Maloney; E. Worley (Microelectron. Reliab., 2001)

Issues in Deep Submicron State-of-the-Art ESD Design (Tutorial Abstract). - Charvaka Duvvury (ISQED, 2002)

Development of substrate-pumped nMOS protection for a 0.13 mum technology. - Craig Salling; Jerry Hu; Jeff Wu 002; Charvaka Duvvury; Roger Cline; Rith Pok (Microelectron. Reliab., 2002)

Latchup in voltage tolerant circuits: a new phenomenon. - Jorge Salcedo-Suñer; Charvaka Duvvury; Roger Cline; Alfonso Cadena-Hernandez (Microelectron. Reliab., 2004)

Trends and challenges to ESD and Latch-up designs for nanometer CMOS technologies. - Gianluca Boselli; Charvaka Duvvury (Microelectron. Reliab., 2005)

Circuit design issues in multi-gate FET CMOS technologies. - Christian Pacha; Klaus von Arnim; Thomas Schulz; Weize Xiong; Michael Gostkowski; Gerhard Knoblinger; Andrew Marshall; Thomas Nirschl; Jörg Berthold; Christian Russ; Harald Gossner; Charvaka Duvvury; et al. (ISSCC, 2006)

Gate oxide failures due to anomalous stress from HBM ESD testers. - Charvaka Duvvury; Robert Steinhoff; Gianluca Boselli; Vijay Reddy; Hans Kunz; Steve Marum; Roger Cline (Microelectron. Reliab., 2006)

System efficient ESD design. - Harald Gossner; Charvaka Duvvury (Microelectron. Reliab., 2015)

Analysis of VF-TLP ESD Measurements Using Machine Learning. - Seyed Hossein Hosseini; Mehrdad Nourani; Theo Smedes; Charvaka Duvvury (ISQED, 2025)